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pc card controller compliant with pcmcia 2.1/jeida 4.2 rf5c296/rf5c396l/RB5C396/rf5c396 electronic devices division no.ea-028-9804 application manual
no tice 1. the products and the product specifications described in this application manual are subject to change or dis - continuation of production without notice for reasons such as improvement. therefore, before deciding to use the products, please refer to ricoh sales representatives for the latest information thereon. 2. this application manual may not be copied or otherwise reproduced in whole or in part without prior written con - sent of ricoh. 3. please be sure to take any necessary formalities under relevant laws or regulations before exporting or other - wise taking out of your country the products or the technical information described herein. 4. the technical information described in this application manual shows typical characteristics of and example application circuits for the products. the release of such information is not to be construed as a warranty of or a grant of license under ricoh's or any third party's intellectual property rights or any other rights. 5. the products listed in this document are intended and designed for use as general electronic components in standard applications (office equipment, computer equipment, measuring instruments, consumer electronic products, amusement equipment etc.). those customers intending to use a product in an application requiring extreme quality and reliability, for example, in a highly specific application where the failure or misoperation of the product could result in human injury or death (aircraft, spacevehicle, nuclear reactor control system, traffic control system, automotive and transportation equipment, combustion equipment, safety devices, life support system etc.) should first contact us. 6. we are making our continuous effort to improve the quality and reliability of our products, but semiconductor products are likely to fail with certain probability. in order prevent any injury to persons or damages to property resulting from such failure, customers should be careful enough to incorporate safety measures in their design, such as redundancy feature, fire-containment feature and fail-safe feature. we do not assume any liability or responsibility for any loss or damage arising from misuse or inappropriate use of the products. 7. anti-radiation design is not implemented in the products described in this application manual. 8. please contact ricoh sales representatives should you have any questions or comments concerning the prod - ucts or the technical information. june 1995
r f5c296/rf5c396l/RB5C396/rf5c396 applica tion manu al contents outline ...................................................................................................... 1 fea tures ................................................................................................... 1 applica tions ............................................................................................. 2 pin configura tion (rf5c296) ...................................................................... 3 pin assignments (rf5c296) ......................................................................... 4 pin configura tion (rf5c396l/rf5c396) ......................................................... 5 pin assignments (rf5c396l/rf5c396) ............................................................ 6 pin configura tion (RB5C396) ...................................................................... 8 pin assignments (RB5C396) ......................................................................... 8 pin description ...................................................................................... 11 1. isa bus interf ace ......................................................................................... 11 2. card slot interf ace ........................................................................................ 13 3. other control pins ........................................................................................ 15 4. p o w er and ground supply pins ......................................................................... 16 block dia gram ....................................................................................... 17 functional description ....................................................................... 18 1. address mapping ......................................................................................... 18 2. p o w er management ...................................................................................... 19 3. mix ed v oltage oper ation ................................................................................. 19 4. address mapping ......................................................................................... 21 5. bus sizing .................................................................................................. 21 6. inter nal register access ................................................................................ 22 7. plur al slots system ....................................................................................... 23 8. pcmcia-a t a mode ....................................................................................... 24 9. dma mode ................................................................................................. 25 internal registers ............................................................................... 27 1.chip control ................................................................................................ 27
2. i/o mapping ................................................................................................ 36 3. memor y mapping ......................................................................................... 38 4. expansion function ....................................................................................... 41 5. i/o address remapping .................................................................................. 42 6. summar y of inter nal register ........................................................................... 44 hard w are design considera tions ..................................................... 46 1. initial v alue setting pins ................................................................................. 46 2. connections to system bus ............................................................................. 47 3. connections to pcmcia slot ............................................................................ 50 4. connections to p o w er supply system ................................................................. 51 5. connecting multiple units of rf5c296 or rf5c396 ................................................. 53 softw are design considera tions ..................................................... 54 1. confir mation of access to inter nal registers .......................................................... 54 2. identification of pc card t ypes ......................................................................... 54 3. address mapping and address windo w setting ...................................................... 54 4. interr upt processing ...................................................................................... 62 5. card slot pin status indication and register setting ................................................. 65 absolute maximum ra tings ................................................................. 70 dc chara cteristics .............................................................................. 71 a c chara cteristics ............................................................................... 73 1. 8/16bit memor y cycle .................................................................................... 73 2. 8/16bit i/o cycle .......................................................................................... 76 3. inter nal 8bits register access cycle ................................................................... 79 4. interr upt, ring indicate speak er ........................................................................ 80 5. reset from po wergood .............................................................................. 81 6. dma read cycle timing ................................................................................. 82 7. dma wr ite cycle timing ................................................................................. 83 8. dma request timing ..................................................................................... 84 b us system .............................................................................................. 85 suppor t envir onment ........................................................................... 85 p a cka ge dimensions .............................................................................. 86
1 rf5c296/rf5c396l/RB5C396/rf5c396 the rf5c296, the rf5c396l, the RB5C396, and the rf5c396 are enhanced version of the rf5c266 and rf5c366, lsis functioning as controllers for interfacing ic memory cards, modems, and i/o cards, such as hdds, to system buses in compliance with the pcmcia2.1 or jeida4.2 standard. these controller lsis can be used to configure an isa bus system which supports pc cards. the rf5c296 supports one pc card slot while the rf5c396l, the RB5C396 and the rf5c396 support two pc card slots. incorporating a buffer and a transceiver, each of these devices can be directly coupled to the isa system bus and the pc card slots. the devices are also capable of providing an independent power supply of 3.3v or 5v for each slot interface, system bus, and core logic. further, they effect substantial space savings through implementa - tion in slimline packages (i.e. the 144pin lqfp for the rf5c296, the 208pin lqfp for the rf5c396l, the 256pin pbga for the RB5C396 and the 208pin qfp for the rf5c396). unless otherwise noted, the rf5c396l, the RB5C396 and the rf5c396 are collectively referred to as the rf5c396 in this manual. compliant with pcmca2. 1 / jeid a4.2 pc card contr oller outline fea tures ?enhanced version of rf5c266/rf5c366 ?dma mode support ?enhanced power management ?inpack# pin support ?available in thin (t=1.5mm) lqfp and pbga ?compliant with pcmcia2.1/jeida4.2 ?i82365sl b_step compatible register set ?direct connection to pcmcia2.1/jeid4.2 pc card slot ?easy host interface using isa i/o addresses 3e0h, 3e1h ?direct connection to isa bus ?programmable irqs to level mode or edge trigger mode ?enhanced power management based on socket and window inactivity ?pcmcia-at-a disk interface support ?8bit cycles follow sbhe# independent of programmed window size ?5 programmable memory windows per slot ?2 programmable i/o windows per slot ?3.3v & 5v mixed voltage operation ?dma mode support
rf5c296/rf5c396l/RB5C396/rf5c396 2 ?pc (notebook type, pen-based type and palm top type) ?docking station ?pda ?handy terminal ?packages ?rf5c296 144pin lqfp (t=1.7mm) ?rf5c396l 208pin lqfp (t=1.7mm) ?RB5C396 256pin pbga (2 3 23) ?rf5c396 208pin qfp applica tions
rf5c296/rf5c396l/RB5C396/rf5c396 3 i r q 3 s a 7 i r q 4 s a 8 i r q 5 s a 9 s a 1 0 i r q 7 s a 1 1 s a 1 2 r e f r e s h # s a 1 3 s a 1 4 s a 1 5 s a 1 6 i o r # i o w # a e n i o c h r d y g n d s d 0 s d 1 z e r o w s # s d 2 g n d s d 3 v c c a t s d 4 s d 5 i r q 9 s d 6 s d 7 p o w e r g o o d s p k r o u t # i n t r # r e s e t d r v v c c 5 e n # v p p _ e n 0 v p p _ e n 1 5 v d e t / g p i r i _ o u t # v c c 3 e n # c s # r e g # c d 3 c d 1 # c d 4 c d 1 1 c d 5 c d 1 2 c d 6 i n p a c k # c d 1 3 v c c s l o t c d 7 g n d c d 1 4 c e 1 # c d 1 5 c a 1 0 c e 2 # o e # c a 1 1 c i o r d # c a 9 c i o w r # c a 8 c a 1 7 c a 1 3 c a 1 8 c a 1 4 c a 1 9 s a 6 s a 5 s a 4 b a l e s a 3 s a 2 s y s c l k s a 1 s a 0 m e m c s 1 6 # s b h e # i o c s 1 6 # l a 2 3 g n d s d 1 5 c d 2 # w p / i o i s 1 6 # c d 1 0 c d 2 c d 9 c d 1 c d 8 c d 0 b v d 1 / s t s c k g # c a 0 b v d 2 / s p k r # c a 1 c a 2 g n d c a 3 w a i t # g n d c a 4 v c c s l o t r e s e t c a 5 c a 6 c a 2 5 c a 7 c a 2 4 c a 1 2 c a 2 3 c a 1 5 c a 2 2 c a 1 6 c a 2 1 r d y / b s y # c a 2 0 w e # / p g m # i r q 1 0 l a 2 2 i r q 1 1 l a 2 1 v c c i r q 1 2 l a 2 0 i r q 1 5 l a 1 9 i r q 1 4 l a 1 8 l a 1 7 m e m r # m e m w # s d 8 s d 9 s d 1 0 g n d s d 1 1 v c c a t s d 1 2 s d 1 3 s d 1 4 7 0 6 0 5 0 4 0 1 0 0 9 0 8 0 v c c _ a t v c c _ a t v c c _ c o r e v c c _ s l o t 1 1 0 1 2 0 1 3 0 1 4 0 1 4 4 1 1 0 2 0 3 0 pin configura tion ?rf5c296 pin assignments (top view) * ) cd1# and cd2# are powered by vcc_at
rf5c296/rf5c396l/RB5C396/rf5c396 4 pin assignments ?rf5c296 pin no. symbol pin no. symbol pin no. symbol pin no. symbol 1 vcc5en# 37 we#/pgm# 73 sd14 109 irq3 2 vpp_en0 38 ca20 74 sd13 110 sa7 3 vpp_en1 39 rdy/bsy# 75 sd12 111 irq4 4 5vdet/gpi 40 ca21 76 vccat 112 sa8 5 riout# 41 ca16 77 sd11 113 irq5 6 vcc3en# 42 ca22 78 gnd 114 sa9 7 cs# 43 ca15 79 sa10 115 sa10 8 reg# 44 ca23 80 sd9 116 irq7 9 cd3 45 ca12 81 sd8 117 sa11 10 cd1# 46 ca24 82 memw# 118 sa12 11 cd4 47 ca7 83 memr# 119 refresh# 12 cd11 48 ca25 84 la17 120 sa13 13 cd5 49 ca6 85 la18 121 sa14 14 cd12 50 ca5 86 irq14 122 sa15 15 cd6 51 reset 87 la19 123 sa16 16 inpack# 52 vccslot 88 irq15 124 ior# 17 cd13 53 ca4 89 la20 125 iow# 18 vccslot 54 gnd 90 irq12 126 aen 19 cd7 55 wait# 91 vcc 127 iochrdy 20 gnd 56 ca3 92 la21 128 gnd 21 cd14 57 gnd 93 irq11 129 sd0 22 ce1# 58 ca2 94 la22 130 sd1 23 cd15 59 ca1 95 irq10 131 zerows# 24 ca10 60 bvd2/spkr# 96 la23 132 sd2 25 ce2# 61 ca0 97 iocs16# 133 gnd 26 oe# 62 bvd1/stschg# 98 sbhe# 134 sd3 27 ca11 63 cd0 99 memcs16# 135 vccat 28 ciord# 64 cd8 100 sa0 136 sd4 29 ca9 65 cd1 101 sa1 137 sd5 30 ciowr# 66 cd9 102 sysclk 138 irq9 31 ca8 67 cd2 103 sa2 139 sd6 32 ca17 68 cd10 104 sa3 140 sd7 33 ca13 69 wp/iois16# 105 bale 141 powergood 34 ca18 70 cd2# 106 sa4 142 spkrout# 35 ca14 71 sd15 107 sa5 143 intr# 36 ca19 72 gnd 108 sa6 144 resetdrv * ) i : active ?ow?signals are indicated by ??
rf5c296/rf5c396l/RB5C396/rf5c396 5 pin configura tion ?rf5c396l/rf5c396 1 5 6 1 5 0 1 4 0 1 3 0 1 2 0 1 1 0 l a 2 3 i o c s 1 6 # s b h e # m e m c s 1 6 # s a 0 s a 1 s y s c l k s a 2 s a 3 b a l e s a 4 s a 5 s a 6 i r q 3 s a 7 i r q 4 s a 8 i r q 5 s a 9 s a 1 0 i r q 7 s a 1 1 s a 1 2 r e f r e s h # s a 1 3 s a 1 4 s a 1 5 s a 1 6 i o r # i o w # b a e n i o c h r d y s d 0 s d 1 z e r o w s # g n d s d 2 s d 3 v c c a t s d 4 s d 5 i r q 9 s d 6 s d 7 p o w e r g o o d s p k r o u t # i n t r # b v p p _ e n 1 b v p p _ e n 0 b v c c 3 e n # b v c c 5 e n # c s # b c a 2 2 b c a 1 6 b c a 2 1 b r d y / b s y # b c a 2 0 b w e # / r g m # b c a 1 9 b c a 1 4 b c a 1 8 b c a 1 3 b c a 1 7 b c a 8 b c i o w # b c a 9 b c i o r d # b c a 1 1 v c c s l o t # 1 b o e # b c e 2 # b c a 1 0 b c d 1 5 b c e 1 # b c d 1 4 b c d 7 b c d 1 3 g n d b c d 6 b c d 1 2 b c d 5 b c d 1 1 b c d 4 b c d 1 # b c d 3 b r e g # g n d a c d 2 # a w p a c d 1 0 a c d 2 a c d 9 a c d 1 a c d 8 a c d 0 a b v d 1 a c a 0 a b v d 2 a c a 1 a c a 2 a i n p a c k # a c a 3 a w a i t # a c a 4 i r q 1 0 l a 2 2 i r q 1 1 l a 2 1 i r q 1 2 l a 2 0 i r q 1 5 l a 1 9 i r q 1 4 l a 1 8 l a 1 7 m e m r # m e m w # s d 8 s d 9 s d 1 0 g n d s d 1 1 v c c a t s d 1 2 s d 1 3 s d 1 4 s d 1 5 r i _ o u t # b c d 2 # b w p b c d 1 0 b c d 2 b c d 9 b c d 1 b c d 8 b c d 0 b b v d 1 / s t s c h g # b c a 0 b b v d 2 / s p k r # b c a 1 b c a 2 b i n p a c k # b c a 3 v c c s l o t # 1 b w a i t # b c a 4 b r e s b c a 5 b c a 6 g n d b c a 2 5 b c a 7 b c a 2 4 b c a 1 2 b c a 2 3 b c a 1 5 a v p p _ e n 1 a v p p _ e n 0 a 5 v d e t / a g p 1 a v c c 3 e n # a v c c 5 e n # b 5 v d e t / b g p 1 r e s e t d r v a r e g # a c d 3 a c d 1 # a c d 4 a c d 1 1 a c d 5 a c d 1 2 a c d 6 a c d 1 3 a c d 7 a c d 1 4 a c e 1 # a c d 1 5 a c a 1 0 a c e 2 # a o e # v c c s l o t # 0 a c a 1 1 a c i o r d # v c c a c a 9 a c i o w r # a c a 8 g n d a c a 1 7 a c a 1 3 a c a 1 8 a c a 1 4 a c a 1 9 a w e # / p g m # a c a 2 0 a r d y / b s y # a c a 2 1 a c a 1 6 a c a 2 2 a c a 1 5 a c a 2 3 a c a 1 2 a c a 2 4 a c a 7 a c a 2 5 a c a 6 a c a 5 a r e s e t v c c s l o t # 0 1 1 6 0 1 7 0 1 8 0 1 9 0 2 0 0 2 0 8 1 0 4 1 0 0 9 0 8 0 7 0 6 0 v c c _ s l o t # 0 v c c _ c o r e v c c _ a t v c c _ s l o t # 1 3 0 4 0 5 2 2 0 1 0 v c c _ s l o t # 0 * ) acd1# ,acd2# ,bcd1#,bcd2# are powered by vcc_at
rf5c296/rf5c396l/RB5C396/rf5c396 6 ?rf5c396l/rf5c396 pin no. symbol pin no. symbol pin no. symbol pin no. symbol 1 avpp_en1 37 awe#/pgm# 73 bcd1# 109 bca7 2 avpp_en0 38 aca20 74 bcd4 110 bca25 3 a5vdet/agpi 39 ardy/bsy# 75 bcd11 111 gnd 4 avcc3en# 40 aca21 76 bcd5 112 bca6 5 avcc5en# 41 aca16 77 bcd12 113 bca5 6 b5vdet/bgpi 42 aca22 78 bcd6 114 breset 7 resetdrv 43 aca15 79 gnd 115 bca4 8 areg# 44 aca23 80 bcd13 116 bwait# 9 acd3 45 aca12 81 bcd7 117 vccslot#1 10 acd1# 46 aca24 82 bcd14 118 bca3 11 acd4 47 aca7 83 bce1# 119 binpack# 12 acd11 48 aca25 84 bcd15 120 bca2 13 acd5 49 aca6 85 bca10 121 bca1 14 acd12 50 aca5 86 bce2# 122 bbvd2/spkr# 15 acd6 51 areset 87 boe# 123 bca0 16 acd13 52 vccslot#0 88 vccslot#1 124 bbvd1/stschg# 17 acd7 53 aca4 89 bca11 125 bcd0 18 acd14 54 await# 90 bciord# 126 bcd8 19 ace1# 55 aca3 91 bca9 127 bcd1 20 acd15 56 ainpack# 92 bciowr# 128 bcd9 21 aca10 57 aca2 93 bca8 129 bcd2 22 ace2# 58 aca1 94 bca17 130 bcd10 23 aoe# 59 abvd2/spkr# 95 bca13 131 bwp/iois16# 24 vccslot#0 60 aca0 96 bca18 132 bcd2# 25 aca11 61 abvd1/stschg# 97 bca14 133 riout# 26 aciord# 62 acd0 98 bca19 134 sd15 27 vcc 63 acd8 99 bwe#/pgm# 135 sd14 28 aca9 64 acd1 100 bca20 136 sd13 29 aciowr# 65 acd9 101 brdy/bsy# 137 sd12 30 aca8 66 acd2 102 bca21 138 vccat 31 gnd 67 acd10 103 bca16 139 sd11 32 aca17 68 awp/iois16# 104 bca22 140 gnd 33 aca13 69 acd2# 105 bca15 141 sd10 34 aca18 70 gnd 106 bca23 142 sd9 35 aca14 71 breg# 107 bca12 143 sd8 36 aca19 72 bcd3 108 bca24 144 memw# pin assignments
rf5c296/rf5c396l/RB5C396/rf5c396 7 pin no. symbol pin no. symbol pin no. symbol pin no. symbol 145 memr# 161 sa0 177 irq7 193 sd2 146 la17 162 sa1 178 sa11 194 sd3 147 la18 163 sysclk 179 sa12 195 vccat 148 irq14 164 sa2 180 refresh# 196 sd4 149 sa19 165 sa3 181 sa13 197 sd5 150 irq15 166 bale 182 sa14 198 irq9 151 la20 167 sa4 183 sa15 199 sd6 152 irq12 168 sa5 184 sa16 200 sd7 153 la21 169 sa6 185 ior# 201 powergood 154 irq11 170 irq3 186 iow# 202 spkrout# 155 la22 171 sa7 187 aen 203 intr# 156 irq10 172 irq4 188 iochrdy 204 bvpp_en1 157 la23 173 sa8 189 sd0 205 bvpp_en0 158 iocs16# 174 irq5 190 sd1 206 bvcc3en# 159 sbhe# 175 sa9 191 zerows# 207 bvcc5en# 160 memcs16# 176 sa10 192 gnd 208 cs# * ) i : active ?ow?signals are indicated by ??
rf5c296/rf5c396l/RB5C396/rf5c396 8 pin configura tion ?RB5C396 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 : g n d a b c d e f g h j k l m n p r t pin assignments pin no. symbol pin no. symbol pin no. symbol pin no. symbol a1 la22 b1 iocs16# c1 sysclk d1 bale a2 la21 b2 irq11 c2 sa2 d2 sa5 a3 la19 b3 irq12 c3 sbhe# d3 memcs16# a4 la17 b4 irq14 c4 irq15 d4 sa1 a5 sd8 b5 memr# c5 la18 d5 irq10 a6 sd11 b6 sd9 c6 sd10 d6 memw# a7 sd14 b7 sd12 c7 sd13 d7 gnd a8 bcd2# b8 sd15 c8 riout# d8 vccat a9 bcd9 b9 bcd2 c9 bwp/iois16 # d9 bcd10 a10 bcd0 b10 bcd8 c10 bcd1 d10 bca0 a11 bca1 b11 bbvd2/spkr# c11 bbvd1/stschg# d11 bca2 a12 bca3 b12 binpack# c12 bwait# d12 bca5 a13 breset b13 bca4 c13 bca24 d13 bca7 a14 bca25 b14 bca6 c14 bca12 d14 bca19 a15 bca23 b15 bca21 c15 bca20 d15 bca18 a16 bca16 b16 brdy/bsy# c16 bca14 d16 bca17 ?RB5C396
rf5c296/rf5c396l/RB5C396/rf5c396 9 pin no. symbol pin no. symbol pin no. symbol pin no. symbol e1 irq3 g1 irq7 j1 sa16 l1 sd1 e2 sa7 g2 sa11 j2 iow# l2 sd2 e3 sa6 g3 sa12 j3 ior# l3 zerows# e4 sa3 g4 sa9 j4 gnd l4 sd4 e5 la23 g5 sa4 j5 gnd l5 intr# e6 la20 g6 gnd j6 gnd l6 gnd e7 gnd g7 gnd j7 gnd l7 gnd e8 gnd g8 gnd j8 gnd l8 gnd e9 gnd g9 gnd j9 gnd l9 gnd e10 vccslot#1 g10 gnd j10 gnd l10 gnd e11 gnd g11 gnd j11 gnd l11 gnd e12 bca15 g12 gnd j12 gnd l12 aca2 e13 bca22 g13 bciowr# j13 gnd l13 awp/iois16# e14 bca13 g14 bcd15 j14 bcd6 l14 bcd3 e15 bca8 g15 bcd10 j15 bcd12 l15 breg# e16 bciord# g16 bce1# j16 bcd5 l16 acd2# f1 sa8 h1 refresh# k1 aen m1 sd3 f2 irq5 h2 sa13 k2 sd0 m2 sd5 f3 sa10 h3 sa15 k3 iochrdy m3 sd6 f4 irq4 h4 sa14 k4 vccat m4 cs# f5 sa0 h5 gnd k5 gnd m5 avpp_en1 f6 gnd h6 gnd k6 gnd m6 avcc5en# f7 gnd h7 gnd k7 gnd m7 acd4 f8 gnd h8 gnd k8 gnd m8 gnd f9 gnd h9 gnd k9 gnd m9 gnd f10 gnd h10 gnd k10 gnd m10 gnd f11 gnd h11 gnd k11 gnd m11 aca7 f12 bwe# h12 gnd k12 gnd m12 aca4 f13 bca9 h13 vccslot#1 k13 acd8 m13 abvd1/stschg# f14 boe# h14 bcd7 k14 bcd11 m14 acd9 f15 bca11 h15 bcd14 k15 bcd4 m15 acd10 f16 bce2# h16 bcd13 k16 bcd1# m16 acd2
rf5c296/rf5c396l/RB5C396/rf5c396 10 pin no. symbol pin no. symbol pin no. symbol pin no. symbol n1 irq9 p1 powergood r1 bvpp_en0 t1 bvcc5en# n2 sd7 p2 bvpp_en1 r2 bvcc3en# t2 avpp_en0 n3 spkrout# p3 a5vdet/agpi r3 areg# t3 resetdrv n4 b5vdet/bgpi p4 avcc3en# r4 acd11 t4 acd1# n5 acd3 p5 acd5 r5 acd6 t5 acd12 n6 acd13 p6 ace1# r6 acd14 t6 acd7 n7 vccslot#0 p7 ace2# r7 aca10 t7 acd15 n8 vcc p8 aciord# r8 aca11 t8 aoe# n9 gnd p9 aciowr# r9 aca8 t9 aca9 n10 aca21 p10 aca13 r10 aca18 t10 aca17 n11 ardy/bsy# p11 aca19 r11 awe# t11 aca14 n12 vccslot#0 p12 aca15 r12 aca16 t12 aca20 n13 aca1 p13 aca24 r13 aca23 t13 aca22 n14 ainpack# p14 aca3 r14 aca25 t14 aca12 n15 acd1 p15 aca0 r15 aca5 t15 aca6 n16 acd0 p16 abvd2/spkr# r16 await# t16 areset
rf5c296/rf5c396l/RB5C396/rf5c396 11 symbol function pin no. rf5c296 rf5c396 * 1 la23 to la17 sa16 to sa0 aen bale sbhe# refresh# sd15 to sd0 ior# iow# memr# memw# iocs16# memcs16# zerows# iochrdy irqn isa bus system address 23 to 17 isa bus system address 16 to 0 address enable. high signal is input in dma mode. address latch enable. this signal latches la23 pin to la17 pin. system bus high byte enable this active low signal indicates that an isa-bus refresh cycle is either requested or in progress. system data bus i/o port read i/o port write memory read memory write 16bit i/o transfer mode chip select 16bit memory transfer mode chip select zero wait state i/o channel ready. this active high signal indi - cates that the accessed device on the isa-bus is ready to terminate the bus cycle. interrupt request signal. irq3, irq4, irq5, irq7, irq9, irq10, irq11, irq12, irq14, irq15. level mode interrupt or edge mode interrupt is programmable. irq12 can be used as a led driver. irq9, irq10, irq11, or irq15 may be used as system side dack#, system side dreq, and system side tc respectively in dma mode. 96,94,92,89,87,85, 84 123,122,121,120, 118,117,115,114, 112,110,108,107, 106,104,103,101, 100 126 105 98 119 71,73,74,75,77,79, 80,81,140,139, 137, 136,134,132, 130,129 124 125 83 82 97 99 131 127 109,111,113,116, 138,95,93,90,86, 88 157,155,153,151, 149,147,146 184,183,182,181, 179,178,176,175, 173,171,169,168, 167,165,164,162, 161 187 166 159 180 134,135,136,137, 139,141,142,143, 200,199,197,196, 194,193,190,189 185 186 145 144 158 160 191 188 170,172,174,177, 198,156,154,152, 148,150 i/o* i i i i i i i/o i i i i o (od) o (od) o (ts) o (ts) o (ts) pin description 1. isa bus interface * ) i : input, o : output, i/o : input/output, o (od) : open drain output, o (ts) : tri-state output. * 1) pin no. of the RB5C396 differ from those of others. refer to ?in configuration? drive 12ma 16ma 16ma 12ma 16ma 8ma
rf5c296/rf5c396l/RB5C396/rf5c396 12 symbol function pin no. rf5c296 rf5c396* 1 sysclk cs# system clock input chip select input. this signal is use for configura - tion cs# control power down mode, in case of dri - ving by the i/o address. 102 7 163 208 i/o * i i * ) i : input, o : output, i/o : input/output, o (od) : open drain output, o (ts) : tri-state output. * 1) pin no. of the RB5C396 differ from those of others. refer to ?in configuration? drive
rf5c296/rf5c396l/RB5C396/rf5c396 13 symbol function pin no. rf5c296 rf5c396 * 2 ca25 to ca0 cd15 to cd8 cd7 to cd0 ce2# ce1# ciord# ciowr# oe# we#/pgm# bvd1 (stschg# /ri#) bvd2 (spkr#) card address output card data bus high byte. input buffer is disabled when card slot power supply is off or card is not inserted. card data bus low byte. input buffer is disabled when card slot power supply is off or card is not inserted. card enable high byte card enable low byte card i/o read card i/o write card output enable card write enable/program the battery voltage detect input 1 on the memory pc card, and card status change#/ring indicate# input on the i/o card. the battery voltage detect input 2 on the memory pc card, and speaker# (digital audio) input on the i/o card. this pin may also be used as card side dreq in dma mode. 48,46,44,42,40,38,36, 34,32,41,43,35,33,45, 27,24,29,31,47,49,50, 53,56,58,59,61 23,21,17,14,12,68,66, 64 19,15,13,11,9,67,65,63 slot#0 : 48,46,44,42,40,38,36, 34,32,41,43,35,33,45, 25,21,28,30,47,49,50, 53,55,57,58,60 slot#1 : 110,108,106,104,102, 100,98,96,94,103,105, 97,95,107,89,85,91,93, 109,112,113,115,118, 120,121,123 slot#0 : 20,18,16,14,12,67,65,63 slot#1 : 84,82,80,77,75,130, 128,126 slot#0 : 17,15,13,11,9,66,64,62 slot#1 : 81,78,76,74,72,129, 127,125 slot#0 : 22 slot#1 : 86 slot#0 : 19 slot#1 : 83 slot#0 : 26 slot#1 : 90 slot#0 : 29 slot#1 : 92 slot#0 : 23 slot#1 : 87 slot#0 : 37 slot#1 : 99 slot#0 : 61 slot# 1 : 124 slot#0 : 59 slot# 1 : 122 i/o* 1 o (ts) i/o(pd) i/o(pd) o (ts) o (ts) o (ts) o (ts) o (ts) o (ts) i i 25 22 28 30 26 37 62 60 * 1) i : input, o : output, i/o : input/output, i/o (pd) : input/output with pull-down register, o (ts) : tri-state output. * 2) all card slot interface signal names are pretended with a-(slot#0) and b-(slot#1). for example, aca25 to aca0 are the card address buses to the slot#0. pin no. of the RB5C396 differ from those of others. refer to ?in configuration? 2. car d slot interface drive 8ma 8ma 8ma 8ma 8ma 8ma 8ma 8ma 8ma
rf5c296/rf5c396l/RB5C396/rf5c396 14 symbol function pin no. rf5c296 rf5c396* 2 cd1#, cd2# rdy/bsy# (ireq#) reg# wait# wp (iois16#) reset inpack# card detect input 1 & 2* 3 ready/busy# input on the memory pc card, and ireq# input on the i/o card. when this signal is ??memory access is limited to attribute memory. during normal access for i/o, this signal must be kept ?? during dma cycle, this signal must be kept ?? this pin may also be used as card side dack in dma mode. bus cycle wait input from pc card write protect switch input on the memory pc card and, iois16# is asserted by pc card when the i/o cycle is 16bit on the i/o. this pin may also be used as card side dreq in dma mode. card reset output input acknowledge. ??is output to inpack# on the pcmcia bus only when i/o ports accessed during i/o signal read are enabled on pc cards that support this signal. when inpack# signal is enabled for rf5c296/rf5c396, i/o signal read data will be output to the system only when the inpack# signal is enabled. this pin may also be used as card side dreq in dma mode. 10,70 39 8 55 69 51 16 slot#0 : 10,69 slot#1 : 73,132 slot#0 : 39 slot#1 : 101 slot#0 : 8 slot#1 : 71 slot#0 : 54 slot#1 : 116 slot#0 : 68 slot#1 : 131 slot#0 : 51 slot#1 : 114 slot#0 : 56 slot#1 : 119 i/o* 1 i i o(ts) i i o(ts) i * 1) i : input, o : output, i/o : input/output, o (ts) : tri-state output. * 2) all card slot interface signal names are pretended with a-(slot#0) and b-(slot#1). for example, aca25 to aca0 are the card address buses to the slot #0. pin no. of the RB5C396 differ from those of others. refer to "pin configuration". * 3) cd1# and cd2# are powered by vcc_at instead of vcc_slot because hot plug-in/out is supported during card slot power is off. drive 4ma 4ma
rf5c296/rf5c396l/RB5C396/rf5c396 15 symbol function pin no. rf5c296 rf5c396* 2 powergood resetdrv spkrout# ri_out# intr# 5vdet/gpi vcc5en# vcc3en# vpp_en0 vpp_en1 powergood input. connect to gnd if not used. reset drive input. this active high signal indi - cates main system cold reset. speaker output. passes through spkr# from an i/o card. ring indicate output. passes through ri_out# from an i/o card. interrupt request output 5v detect input/general purpose input, on gpi enable. irq generation is programmable when transition occurs. basically user can use this input arbitrarily. this pin shall be connected to the vsi# in the card slot for use as 5v detect input. power control (5v) power control (3.3v) program power supply control 0 (vpp_vcc) program power supply control 1 (vpp_pgm) 141 144 142 5 143 4 1 6 2 3 201 7 202 133 203 slot#0 : 3 slot#1 : 6 slot#0 : 5 slot#1 : 207 slot#0 : 4 slot#1 : 206 slot#0 : 2 slot#1 : 205 slot#0 : 1 slot#1 : 204 i/o* 1 i i (pd) o (ts)* 3 o (t s ) * 3 o (ts)* 3 i (pu) o o o o 3. other contr ol pins * 1) i : input, o : output, i/o : input/output, i (pu) : input with pull-up register, i (pd) : input with pull-down register, o (ts) : tri-state output. * 2) all card slot interface signal names are pretended with a-(slot#0) and b-(slot#1). for example, aca25 to aca0 are the card address buses to the slot #0. pin no. of the RB5C396 differ from those of others. refer to ?in configuration? * 3) applicable to only rf5c296. drive 4ma 4ma 4ma 4ma 4ma 4ma 4ma
rf5c296/rf5c396l/RB5C396/rf5c396 16 symbol function pin no. rf5c296 rf5c396* 1 vcc vccat vccslot gnd vcc for core logic vcc for isa interface signals vcc for card interface signals ground pin 91 76, 135 18, 52 20,54,57,72,78, 128,133 27 138, 195 slot#0 : 24,52 slot#1 : 88,117 31,70,79,111,140, 192 4. p o wer and gr ound suppl y pins * 1) all card slot interface signal names are pretended with a-(slot#0) and b-(slot#1). for example, aca25 to aca0 are the card address buses to the slot#0. pin no. of the RB5C396 differ from those of others. refer to ?in configuration?
rf5c296/rf5c396l/RB5C396/rf5c396 17 block dia gram s d 1 5 - s d 0 a e n r e f r e s h # l a 2 3 - l a 1 7 s a 1 6 - s a 0 c s # b a l e s b h e i o r # , i o w # m e m r # , m e m w # m e m c s 1 6 # z e r o w s # , i o c h r d y i r q n ( d r e q , d a c k # , t c ) p o w e r g o o d r e s e t d r v s p k r o u t # r i _ o u t i n t r # 5 v d e t / g p i i s a b u s c o n t r o l l o g i c a d d r e s s m a p p i n g l o g i c a d d r e s s b u f f e r s l o t # 1 ( r f 5 c 3 9 6 ) d a t a b u s b u f f e r c a r d s t r o b e s p o w e r c o n t r o l s o c k e t c o n t r o l a n d s t a t u s s l o t # 0 c a 1 1 t o c a 0 c a 2 5 t o c a 1 2 c d 1 5 t o c d 8 c d 7 t o c d 0 c e 1 # , c e 2 # c i o r d # , c i o w r # o e # , w e # ( t c # ) r e g # ( d a c k # ) v p p _ e n 0 v p p _ e n 1 v c c 5 e n # v c c 3 e n # b v d 1 ( s t s c h g # , r i # ) b v d 2 ( s p k r # , d r e q ) c d 1 # , c d 2 # r d y / b s y # ( i r e q # ) w a i t # w p ( i o i s 1 6 # , d r e q ) r e s e t i n p a c k # ( d r e q ) m i s c . c o n t r o l i o c s 1 6 # s y s c l k
rf5c296/rf5c396l/RB5C396/rf5c396 18 rf5c296 (rf5c396) is a controller for supporting one (two) card slot compliant to pcmcia2.1/jeida4.2 68pin standard. direct connection to the card slot is allowed due to the complete buffering of signals to the card. rf5c296/rf5c396 can also interface directly to the isa bus. functional description each socket has five independently enabled and controlled system memory address mapping windows and two independently enabled and controlled system i/o address mapping windows. some portions of 64mb common memory and 64mb attribute memory spaces on the pc cards can be mapped into the smaller 16mb isa address space. mapping of each system memory window can start and stop on any 4kb boundary of isa system memory above 64kb except for i/o address space of 0000h to 0ffffh by setting the system memory mapping start register, sys - tem memory mapping stop register, and card memory offset register. the summation result (in 2's complement) of the value in the card memory offset register and isa system address value will result in the memory card address. each window has independent control of data bus size, the number of wait cycles, and the selection of common memory area or attribute memory area. each i/o window can be mapped with 1byte resolution between 0000h to 0ffffh in the isa system address space by setting the i/o start address register and the i/o stop address register. i/o mapping is not allowed during the dma cycle. p c m c i a s o c k e t m e m o r y a d d r e s s s p a c e i s a m e m o r y a d d r e s s s p a c e s y s t e m m e m o r y w i n d o w : m e m o r y m a p e n d a d d r e s s d 0 0 0 : f f f f h m e m o r y m a p s t a r t a d d r e s s d 0 0 0 : 0 0 0 0 h m a p p i n g 3 f f f f f f h = 6 4 m b r e s u l t i n g p c m c i a s o c k e t m e m o r y w i n d o w : e n d a d d r e s s 0 0 0 f f f f h s t a r t a d d r e s s 0 0 0 0 0 0 0 h m e m o r y m a p a d d r e s s o f f s e t = 3 f 3 0 x x x h = 0 0 d 0 0 0 0 h ( t w o ' s c o m p l e m e n t w h e n n e g a t i v e o f f s e t ) 1. ad dress mapping
rf5c296/rf5c396l/RB5C396/rf5c396 19 when card slot is empty or the power supply is off, each card slot has independently power management because each slot has its own buffers and transceivers. in order to achieve the low power consumption especially for the notebook pcs, each address mapping circuit will be powered down when it is not activated. in addition to the function, setting the power down bit in the global control register to ??enables the rf5c296/rf5c396 to go into the power down mode. there is a single power down control bit which can be written with either a slot#0 or slot#1 global control register index. setting this bit to ??goes into the power down mode. even in the power down mode, rf5c296/rf5c396 can generate a card status change interrupt and pc card interrupt for i/o cards. the rf5c296/rf5c396 can also generate the ri_out# signal when configured for ring indicate resume from i/o cards. in this power down mode, the following isa bus signals will be ignored. sd[15 : 0], la[23 : 17], sa[16 : 0], iord#, iowr#, aen, bale, sysclk, memw#, memr#, sbhe# there are three/four different power nets ; vcc for isa bus interface, vcc for core logic, vcc for card slot interface ; to be handled in rf5c296/rf5c396. each of these power nets can be independently running at 3.3v or 5v. all of the voltage combinations listed on the next page are supported. rf5c296/rf5c396 can operate even with the single power supply of 5v or 3.3v i s a b u s v c c _ a t v c c _ c o r e v c c _ s l o t # 0 s l o t # 0 s l o t # 0 i n t e r f a c e s l o t # 1 i n t e r f a c e s l o t # 1 v c c _ s l o t # 1 c o r e l o g i c i s a b u s i n t e r f a c e r f 5 c 2 9 6 / r f 5 c 3 9 6 2. p o wer mana g ement 3. mix ed v olta g e operation
v c c 3 e n # v c c 5 e n # v c c s l o t # 5 v d e t / g p i r f 5 c 2 9 6 / r f 5 c 3 9 6 p o w e r c o n t r o l c i r c u i t s p c m c i a c a r d s l o t v c c v s 1 # * 2 * 2 rf5c296/rf5c396l/RB5C396/rf5c396 20 core (vcc_core) isa bus interface (vcc_at) 5v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 5v 5v 3.3v 5v 3.3v 5v 5v 3.3v 3.3v 5v 5v 5v 3.3v 3.3v 5v 3.3v 5v 3.3v 5v 5v 5v 5v 5v 3.3v 3.3v 3.3v 3.3v when 5vdet/gpi pin is connected to pcmcia card slot pin #43 (vs1#) as shown in the figure, the following should be considered. (1) interface status register bit7* 1 indicate inverted 5vdet/gpi. (2) card detect and control register bit2* 1 (gpi enable) must be kept ?? mixed voltage operation card slot#0 (vcc_slot#0) card slot#1 (vcc_slot#1) * 1) refer to page 27 ?nternal resisters * 2) as shown in the above table, the rf5c296 and the rf5c396 allow sharing of a power supply between their vcc_slots and the pccard slots, provided that the vcc_core should be set to 3.3v.
rf5c296/rf5c396l/RB5C396/rf5c396 21 to prevent any conflict between interrupt request signals derived from the rf5c296 or the rf5c396 and from any other device, the pc card status change, such as fluctuations in the voltage of the battery for the pc card and insertion or removal of the pc card into or from the pc card slot, as well as interrupt request signals (ireq#) derived from the i/o cards can be assigned to one of the ten interrupt lines for ten interrupt request signals (irq15, irq14, irq12, irq11, irq10, irq9, irq7, irq5, irq4, and irq3). these interrupt requests are programmable to the level mode or the edge trigger mode. in addition to steering irqn output, intr# output is also used as an interrupt output. the intr# pin signal is normally input to the extsmi# pin of the intel 386sl to output a low-level pulse having three times the width of the sysclk pulse at the time of interrupt request generation and a high-level pulse at any other time. in addition to these interrupts sources, it is programmable that irqs will be generated when the transition occurs on gpi (general purpose input). if card status change while other card status change interrupt request, second interrupt request pulse is not gen - erated. in this case, the appropriate bit must be set to ??in the card status change register (index : 04h) in the explicit write back acknowledge mode to enable interrupt request recognition by the host system interrupt pro - cessing routine. upon interrupt request recognition, the bit is reset to ?? incidentally, all the bits in the card status change register (index : 04h) are reset to ??when it is read in any other mode than the explicit write back acknowledge mode. irq9, irq10, irq12, irq11 (or irq15) are multi-function pins. in pcmcia-ata mode, irq12 can drive led. in dma mode, irq9, irq10, irq11 (or irq15) work as dack#, dreq, tc. in addition to 16bit bus cycle, rf5c296/rf5c396 supports 8bit bus cycle. the 8bit bus cycle to a pc card can be generated even when the window is configured for 16bit. this means that the combination of sbhe# input and sa0 input override the data size configuration. on 8bit host systems, the sbhe# input must be pulled high (inactive) for proper operation. the following is a truth table of the card enable logic. 4. ad dress mapping 5. bus sizing 16bit window sbhe# a0 ce2# ce1# yes l l l l yes l h l h yes h l h l yes h h h l no l l h l no l h h l no h l h l no h h h l
rf5c296/rf5c396l/RB5C396/rf5c396 22 all of the control registers of the rf5c296/rf5c396 are 8bit width registers and can be accessed using an indi - rect indexing scheme. only two i/o addresses such as (3e1h) and (3e0h) are used to access all control registers. rf5c296/rf5c396 has the external decode mode. in this mode, i/o address is decoded outside and input to cs#. when resetdrv falls, if the level of intr# pin is ??(??, internal decode mode (external decode mode) can be selected. consequently, these operations can be enabled by externally pulling up or down the intr# pin to such a degree as not to affect normal operation. in the internal decode mode, too, the cs# pin should be caused to transition to low level at the time of internal register access (the cs# pin should be caused to transition to high level only in the power down mode). the index register has the bit settings shown below : index register (3e0h) bit7 ?? device#0 ?? device#1 bit6 ?? slot#0 ?? slot#1 bit5 bit4 bit3 bit2 bit1 bit0 register index there are 56 control registers provided for each pc card slot. the index register has bit7 for indicating a device number depending on the status of the spkrout# pin for the rf5c396 or the ri_out# pin for the rf5c296 at the falling edge of the resetdrv pin signal. for the rf5c296, in particular, the index register has bit6 (slot bit) for indicating a device number depending on the status of the spkrout# pin at the falling edge of the resetdrv pin signal. both the spkrout# and ri_out# pins operate in the same manner as the intr# pin described above. the status of the spkrout# pin (for the rf5c396) or the ri_out# pin (for the rf5c296) corresponds to the index range as shown in the tables in ?. plural (three) slot systems?on the next page. note that these pins also require their status control for connecting a single unit of the rf5c296 or the rf5c396. 6. internal register access
rf5c296/rf5c396l/RB5C396/rf5c396 23 as described before, the settings of bit7 and bit6 (slot bit) in the index register depend on the status of the spkrout# pin for the rf5c396 or the ri_out# pin for the rf5c296 and on the status of the the spkrout# pin for the rf5c296, respectively, at the falling edge of the resetdrv pin signal. therefore, 4 slots system can be con - structed using plural rf5c296/rf5c396's without modifying i/o address (3e0h, 3e1h) 1-slot system : one rf5c296 2-slot system : one rf5c396 or two rf5c296 3-slot system : one rf5c396 and one rf5c296, or three rf5c296 4-slot system : two rf5c396, or one rf5c396 and two rf5c296, or four rf5c296 the following tables show the relation between the index range and the status of spkrout# and ri-out# when resetdrv falls. ri_out# vdd vdd gnd gnd spkrout# vdd gnd vdd gnd device bit 0 0 1 1 slot bit 0 1 0 1 index range 00 to 3fh 40 to 7fh 80 to bfh c0 to efh ?rf5c396 spkrout# vdd vdd gnd gnd device bit 0 0 1 1 slot bit 0 1 0 1 index range 00 to 3fh 40 to 7fh 80 to bfh c0 to efh more than five pc card slots can also be supported through external decoding of the a15 to a1 pin signals for input to the cs# pin and thereby setting of any given i/o addresses of the internal registers for the rf5c296 and the rf5c396. notice access to any other index range than is specified at power-on is invalidated while any attempt to read the index register results in a data bus output of high impedance. 7. plural slots system ?rf5c296 7.2 five or more slots 7.1 up to 4 slots
1 gnd gnd 35 gnd gnd 2 cd3 cd3 36 cd1# cd1# 3 cd4 cd4 37 cd11 cd11 4 cd5 cd5 38 cd12 cd12 5 cd6 cd6 39 cd13 cd13 6 cd7 cd7 40 cd14 cd14 7 ce1# ce1# 41 cd15 cd15 8 ca10 ca10 42 ce2# ce2# 9 oe# oe# 43 nc nc 10 ca11 ca11 44 ciord# ciord# 11 ca9 ca9 45 ciowr# ciowr# 12 ca8 ca8 46 ca17 ca17 13 ca13 ca13 47 ca18 ca18 14 ca14 ca14 48 ca19 ca19 15 we# we# 49 ca20 ca20 16 ireq# ireq#( ireq) 50 ca21 * 17 vcc vcc 51 vcc vcc 18 vpp1 vpp1 52 vpp2 vpp2 19 ca16 ca16 53 ca22 * 20 ca15 ca15 54 ca23 * 21 ca12 ca12 55 ca24 * 22 ca7 ca7 56 ca25 * 23 ca6 ca6 57 rfu nc 24 ca5 ca5 58 reset reset 25 ca4 ca4 59 wait# wait# 26 ca3 ca3 60 nc nc 27 ca2 ca2 61 reg# reg# 28 ca1 ca1 62 spkr# led# 29 ca0 ca0 63 stschg# stschg# 30 cd0 cd0 64 cd8 cd8 31 cd1 cd1 65 cd9 cd9 32 cd2 cd2 66 cd10 cd10 33 iois16# iois16# 67 cd2# cd2# 34 gnd gnd 68 gnd gnd rf5c296/rf5c396l/RB5C396/rf5c396 24 rf5c296/rf5c396 supports a pcmcia-ata interface mode. the following table shows the card interface sig - nals when pcmcia-ata mode is configured. pin no. pcmcia i/o interface signal ata interface signal pcmcia i/o interface signal ata interface signal 8. pcmcia-a t a mode * ) the signals are settable in the internal registers of rf5c296/rf5c396. pin no.
rf5c296/rf5c396l/RB5C396/rf5c396 25 setting the bit0 of the mode control register 1 (index=1fh) to ??configures the corresponding card slot to the pcmcia-ata mode. in pcmcia-ata mode, if the bit1 of the mode control register is set to ?? the spkr# input works as an led input and irq12 works as an open drain led output. at this time spkrout# will become inac - tive. bits2 to 6 can be set to specify the values of the ca21 to ca25 pin signals (marked with * ?in the pin definition table in the pcmcia-ata mode on the previous page). in the pcmcia-ata mode, the output ca21 to ca25 pin signals assume the values thus specified by bits2 to 6. bit7 can be set to prevent any conflict between the system floppy disk signal and the card interface signals. when set to ?? bit7 is disabled during reading from an i/o address of 3f7h and 377h on the system data bus. mode control register 1 (index=1fh) bit7 377h, 3f7h disable (in i/o read) bit6 a25 bit5 a24 bit4 a23 bit3 a22 bit2 a21 bit1 led enable bit0 pcmcia- ata mode rf5c296/rf5c396 provide the dma mode for supporting interfacing with external floppy disk units or other dma devices via the pc card slots. setting bit1 of mode control register 3 to ??enables dma mode. the dma data will be transferred to/from dma capable pc card with the isa bus as a dma master. on the dma mode, some of rf5c296/rf5c396 signal pins will be redefined. irq9 will work as dack# input, irq10 will work as dreq output, irq11 (or irq15) will work as tc input. dreq from the pc card can be assigned to one of three pcmcia inputs (iois16#, spkr# or inpack#) by set - ting bit7 and bit6 of mode control register 2. dma transfer between the isa system memory and the i/o card is available in the following two types : 1) dma transfer between the isa system memory and the i/o card 2) dma transfer between memory in the i/o card and the i/o port via the system data bus. notice i s a b u s d r e q d a c k # t c i r q 1 0 i r q 9 i r q 1 1 ( o r 1 5 ) i o i s 1 6 # s p k r # o r i n p a c k # d r e q d a c k # i o i s 1 6 # , s p k r # , o r i n p a c k # r e g # r f 5 c 2 9 6 / f r 5 c 3 9 6 p c c a r d d m a m a d e c o n f i g u r a t i o n r e g # only one slot at a time should be enabled for dma transfer. and dma transfer to/from dma capable pc card may be 8 or 16bit as shown in the bus sizing table of page 21. 9. dma mode
1) irq9, irq10 and irq11 (or irq15) are redefined as dma signals for isa bus. therefore these signals can not be used as interrupt lines. 2) bit5 of general control register must be set to ??to select i/o card. 3) if wp/iois16# is used as dreq, bit4 of interface status register indicates dreq from pc card. 4) if bvd2/spkr# is used as dreq, spkrout# and led output can not be used. 5) if inpack# is used as dreq, bit2 of mode control register 2 must be kept ?? 6) tc input can be assigned to one of two irq signals (irq11 or irq15) by setting bit4 of mode control register . rf5c296/rf5c396l/RB5C396/rf5c396 26 the tc# (terminal count) pin signal input to the pc card becomes active low for output from the oe# pin at a cycle for reading from the pc card (a cycle for writing to the memory) and from the e# pin at a cycle for writing to the pc card (a cycle for reading from the memory). further, the output reg# pin signal is always held at high level during dma transfer. thus, it is easy to distinguish between dma transfer and ordinary bus cycles. namely, the reg# pin signal functions as dma transfer acknowledgment for the pc card. notice on the dma mode
rf5c296/rf5c396l/RB5C396/rf5c396 27 internal registers rf5c396 has the registers both for slot#0 (2) and slot#1 (3). rf5c296 has the registers only for slot#0 (1, 2, 3). the internal registers have default bit settings (immediately after the falling edge of the resetdrv pin signal when the powergood pin signal is set to ?? as enumerated below: index : 00h default value : 1000 0011b read only bit7 to bit6 : these bits indicate the type of pc cards supported by the rf5c296/rf5c396. bit7 0 0 1 1 bit6 0 1 0 1 interface i/o only memory only memory & i/o reserved index : 01h default value : depends on pc card slot status read only bit7 : indicates the state of the reverse of the gpi pin. bit6 : pc card power active. indicates the current power status of the socket. ??shows that power to the socket is off, and ??shows that the power is provided to the socket. bit5 : ready/busy status bit. this bit indicates the busy status when set to ??and the ready status when set to??when the pc card is the memory card. further, this bit specifies reading back of the ireq# pin signal when the pc card is the i/o card. bit4 : memory write protect. indicates the state of the wp pin. memory write accesses to the slot will not be blocked unless the write protect bit in the card memory offset address register high byte is set to ?? 1. chip contr ol * ) in this register, bits7 and 6 identify the type of the pc card controllers while bits3 to 0 indicate revision numbers. if this register is read, can be read back ?3h? bit5 : reserved bit4 : reserved bit3 : revision# : 0 bit2 : revision# : 0 bit1 : revision# : 1 bit0 : revision# : 1 1.1 identification and re vision register* 1.2 interface status register
rf5c296/rf5c396l/RB5C396/rf5c396 28 bit3 : card detect 2. this bit specifies reading back of the input cd2# pin signal in the inverted state. this bit will be set to ??in the presence of the card in the slot when the ic core is connected to the external pull- up resistor because the cd2# pin is connected to the gnd pin inside the card. bit2 : card detect 1. this bit specifies reading back of the input cd1# pin signal in the inverted state. this bit will be set to ??in the presence of the card in the slot when the ic core is connected to the external pull- up resistor because the cd1# pin is connected to the gnd pin inside the card. bit1 to 0 : battery voltage detect 2&1. bits 1 and 0 can be used to specify reading back of the status of the input bvd2 and bvd1 pin signals, respectively, when the pc card is the memory card. bits 1 and 0 can also be used to specify the battery status as shown in the table below: bit0 0 0 1 1 bit1 0 1 0 1 status battery dead battery dead warning battery good for i/o card, bit0 indicates the current status of the (stschg#/ri#) signal from the i/o card when the ring indicate enable bit in the interrupt and general control register is set to ?? index : 02h default value : 0000 0000b read & write bit7 : output enable. when set to ?? this bit specifies high impedance for slot output signals from the following pins : ca [25 : 0], cd [15 : 0], ce1#, ce2#, ciord#, ciowr#, oe#, reg#, reset, and we#. note that the pull-down resistor and input slot signal of the dc [15 : 0] pin remain valid. bit6 : disable resume resetdrv. if bit is set to ??and pwrgood=?? the restable registers of rf5c296/rf5c396 will not be reset. if the resetdrv is a result of a system reset (pwrgood= ??, the reset able registers of rf5c296/rf5c396 will be reset regardless of the setting bit. bit5 : auto power switch enable. when this bit is set to ?? the power control values specified by bits4 to 0 (power control bits) in this register and bit0 in the mixed voltage control register (index : 2fh) are auto - matically output upon setting of both the cd1# and cd2# pin signals to ?? conversely, upon setting of either the cd1# or cd2# pin signal to ?? all the the power control values become inactive. when this bit is set to ?? the power control values specified by bits4 to 0 (power control bits) in this register and bit0 in the mixed voltage control register (index : 2fh) are output regardless of whether the cd1# and cd2# pin signals are set to ??or ?? 1.3 p o wer and resetdr v contr ol register
rf5c296/rf5c396l/RB5C396/rf5c396 29 bit4 to bit0 : p ower control bits. these bits cooperate with bit0 in the mode control register (ind ex : 2f h) to set the vcc3en, vcc5en, vpp_en1, and vpp_en0 pin signals t o ??or ??as show n in the table b elow : bit4 bit3* 1 bit2* 1 bit1 bit0 bit0 of mode control register vcc3en# vcc5en# vpp_en1* 2 vpp_en0* 3 index : 04h default value : 0000 0000h read & write bit 7 t o bit5 : reserved bit4 : gpi change bit. this bit will be set upon generation of any interrupt due to the gpi pin status change. this bit is held at ??unless the gpi enable bit is set to ??in the card detect and general control register. bit3 : card detect change. bit is set to ??when a change has been detected on either the cd#1 or cd2# pin. bit2 : ready change. bit is set to ??when a low to high has been detected on the ready/busy# pin. bit reads ??for i/o cards. bit1 : bit is set to ??when battery warning condition has been detected. for the battery warning condition, see the description of bits1 and 0 in the interface status register (index : 01h). bit reads ??for i/o cards. bit0 : bit is set to ??when battery dead condition has been detected for memory card. for the battery warning condition, see the description of bits1 and 0 in the interface status register (index : 01h). for i/o cards, bit is set to ??if ring indicate enable bit in the interrupt and general control register is set to ??and stschg#/ri# signal from i/o card has been pulled low. this bit reads ??for i/o cards if the ring indicate enable bit in the interrupt and general control register is set to ? . 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 1 0 0 1 1 1 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 0 * 1) bit3 and bit2 : don't care. vccnen# means vcc5en# or vcc3en#, this signal defined by voltage selection. * 2) the settings of bits 3 and 2 are don't care. the settings of the vpp_en1 and vpp_en0 pin signals to ??and ?? ??and ?? ??and ?? and ??and ??specify their connection to no pin, connection to the vcc pin, connection to the vpp pin, and reservation, respectively. 1.4 car d status chang e register
rf5c296/rf5c396l/RB5C396/rf5c396 30 the card status change register contains the status for sources of the card status change interrupt. these sources can be enabled to generate a card status change interrupt by setting the corresponding bit in the card status change interrupt configuration register. there are two ways to reset this register, (1) read card status change register (2) write back ??into the corresponding bit in the card status change register after setting explicit write back card status change acknowledge bit to ??in the global control register. index : 16h default value : 0000 0000b read & write bit7 to bit6 : reserved bit5 : software card detect interrupt. if the card detect enable bit is set to ??in the card status change interrupt configuration register, then writing ??to the software card detect bit in the card detect and general control register will cause a card detect and status change interrupt. the functionality and acknowledgement of this software interrupt will work the same way as the hardware generated interrupt. this bit is always read as ?? bit4 : card detect resume enable. when this bit is set to ?? and once a card detect change has been detect - ed on the cd1# and cd2# inputs, ri-out# output will go ?igh?to ?ow?and bit3 of card status change register will be set to ?? the ri_out# pin signal is held at ??until bit3 is reset to ??in the and status change register. the ri_out# pin signal is not generated up on and detection unless the card detection enable bit is first set to ??in the card status interrupt configuration register (index : 05h). if the card status change is routed to either the intr# and any of irqn signals, the setting of this bit to ??will prevent intr# and irqn signal becoming active as a result of card status change. bit3 : gpi transition control. default value is ?? if this bit is set to ?? a card status change interrupt will be generated when gpi# input goes ??to ?? if this bit is set to ?? a card status change interrupt will be generated when gpi# input goes ??to ?? bit2 : gpi enable. if this bit is set to ?? a card status change interrupt will be generated when gpi# input changes. bit1 : configuration reset enable. if this bit is set to ?? a reset pulse will be generated when both cd1# and cd2# goes ??to ?? this reset pulse reset the following registers. 1.5 car d detect and general contr ol register
rf5c296/rf5c396l/RB5C396/rf5c396 31 interrupt and general control (index : 03h) (except intr# enable bit) address window enable (index : 06h) (except memcs16# decode a23 to a12 bit) i/o control (index : 07h) i/o address n start low byte (index : 08h, 0ch) i/o address n start high byte (index : 09h, 0dh) i/o address n stop low byte (index : 0ah, 0eh) i/o address n stop high byte (index : 0bh, 0fh) system memory address n mapping start low byte (index : 10h, 18h, 20h, 28h, 30h) system memory address n mapping start high byte (index : 11h, 19h, 21h, 29h, 31h) system memory address n mapping stop low byte (index : 12h, 1ah, 22h, 2ah, 32h) system memory address n mapping stop high byte (index : 13h, 1bh, 23h, 2bh, 33h) card memory offset address n low byte (index : 14h,1ch, 24h, 2ch, 34h) card memory offset address n high byte (index : 15h,1dh, 25h, 2dh, 35h) bit0 : 16bit memory delay inhibit. default value is ?? if this bit is set to ?? the falling edge of the control strobes oe# and we# will be generated from the first falling edge of sysclk after the falling edge of memw# or memr# in the 16bit memory cycle. if this bit is set to ?? the control strobes oe# and we# will not be syn - chronously delayed by sysclk.
rf5c296/rf5c396l/RB5C396/rf5c396 32 index : 1eh default value : 0000b read &write this register is not duplicated per slot. this register can be accessed from either slot#0 or slot1# in rf5c396. consequently, access to indexes of 1eh and 5eh means access to the same register. bit7 to bit4 : reserved bit3 : irq14 pulse mode enable. setting this bit to ??and bit 1 (level mode interrupt enable) to ??will enable the rf5c296/rf5c396 to support pulse-mode irq14 interrupt output. bit2 : explicit write back card status change acknowledge bit. setting this bit to ??will require an explicit write of ??to the card status change register bit which indicates an interrupting condition. default value is ?? when this bit is set to ?? the card status change interrupt is acknowledged by reading the card status change register, and the register bits are cleared upon a read. bit1 : in the level mode, the irqn pin signals are held at high impedance until generation of any interrupt caused by the card status change register (index : 04h) or routed by the irqn pin signals from the i/o card. when this bit is set to ?? the irqn pin signals are caused to transition from high impedance to ? upon interrupt generation and reverted to high impedance upon completion of interrupt processing (in the level mode). when this bit is set to ?? the irqn pin signals are caused to transition from ??to ? upon interrupt enabling and from ??to ??upon interrupt generation, and becomes inactive upon completion of interrupt processing (in the edge mode). bit0 : power down bit if this bit is set to ?? then setting cs# to ??will go into the power down mode. during cs# controlled power down, all internal registers are inaccessible, outputs are disabled, and the chip is at minimum power consumption level. irqn and ri_out# will still be active to monitor the card detect and ri# status for resume indication. cs# 0 1 0 1 power down control bit 0 0 1 1 power down mode no no no yes 1.6 global contr ol register
rf5c296/rf5c396l/RB5C396/rf5c396 33 index : 06h default value : 0000 0000b read & write bit7 : i/o window 1 enable. if this bit is set to ?? an i/o access within the i/o address window 1 will inhibit the card enable signal. bit6 : i/o window 0 enable. if this bit is set to ?? an i/o access within the i/o address window 0 will inhibit the card enable signal. bit5 : memcs16# decode a23 to a12. if this bit is set to ?? memcs16# is generated from a decode of a23 to a17. if this bit is set to ?? memcs16# is generated from a decode of a23 to a12. the memcs16# pin signal is out - put within any specified address range whether the pc card is the memory card or the i/o card. bit4 : memory window 4 enable bit. if this bit is set to ?? a memory access within the memory window 4 will inhibit the card enable signal. bit3 : memory window 3 enable bit. if this bit is set to ?? a memory access within the memory window 3 will inhibit the card enable signal. bit2 : memory window 2 enable bit. if this bit is set to ?? a memory access within the memory window 2 will inhibit the card enable signal. bit1 : memory window 1 enable bit. if this bit is set to ?? a memory access within the memory window 1 will inhibit the card enable signal. bit0 : memory window 0 enable bit. if this bit is set to ?? a memory access within the memory window 0 will inhibit the card enable signal. 1.7 ad dress windo w enab le register
rf5c296/rf5c396l/RB5C396/rf5c396 34 index : 03h default value : 0000 0000b read & write bit7 : ring indicate enable. setting this bit to ??for i/o card, the stschg#/ri# signal from the i/o card is used as the status change signal stschg#. the current status of the signal is then available to the read from the interface status register and this signal can be configured as a source for the card status change interrupt. setting this bit to ?? stschg#/ri# signal from the i/o card is used as a ring indicator signal and is passed through to the ri_out# pin. for memory pc card, bit has no function. bit6 : pc card reset#. setting this bit to ??activates the reset signal to the pc card. the reset signal will be active until this bit is set to ?? bit5 : pc card type. setting this bit to ??selects an i/o card. setting this bit to ??selects a memory card. bit4 : intr# enable. setting bit to ??enables the card status change interrupt on the intr# signal. if this bit is set to ?? the card status change interrupt is steered to one of the irqn lines according bits7 through 4 in the card status change interrupt configuration register. bit3 to bit0 : irqn level selection (i/o card only). bit3 bit2 bit1 bit0 irqn selection 0 0 0 0 irq not selected 0 0 1 1 irq3 enabled 0 1 0 0 irq4 enabled 0 1 0 1 irq5 enabled 0 1 1 1 irq7 enabled 1 0 0 1 irq9 enabled 1 0 1 0 irq10 enabled 1 0 1 1 irq11 enabled 1 1 0 0 irq12 enabled 1 1 1 0 irq14 enabled 1 1 1 1 irq15 enabled 1.8 interrupt and general contr ol register
rf5c296/rf5c396l/RB5C396/rf5c396 35 index : 05h default value : 0000 0000b read & write bit7 to bit4 : these bits select the redirection of the card status change interrupt if the interrupt is not selected to intr# pin. intr# enable bit bit3 bit2 bit1 bit0 irqn selection 0 0 0 0 0 irq not selected 0 0 0 1 1 irq3 enabled 0 0 1 0 0 irq4 enabled 0 0 1 0 1 irq5 enabled 0 0 1 1 1 irq7 enabled 0 1 0 0 1 irq9 enabled 0 1 0 1 0 irq10 enabled 0 1 0 1 1 irq11 enabled 0 1 1 0 0 irq12 enabled 0 1 1 1 0 irq14 enabled 0 1 1 1 1 irq15 enabled 1 redirected to intr# bit3 : card detect enable. setting bit to ??enables a card status change interrupt when a change has been detected on cd1# or cd2# signals. bit2 : ready enable. setting this bit to ??enables a card status change interrupt when a ??to ??transition has been detected on ready/busy# signals. this bit is ignored when interface is configured for i/o card. bit1 : battery warning enable. setting this bit to ??enables a card status change interrupt when battery warning condition has been detected. this bit is ignored when interface is configured for i/o card. bit0 : battery dead enable. for memory cards, setting this bit to ??enables a card status change interrupt when a battery dead condition has been detected. for i/o cards, a card status change interrupt will be generated if the stschg#/ri# has been pulled ??assuming ring indicate enable bit (bit7) in interrupt and general control register is set to ?? 1.9 car d status interrupt configuration register
rf5c296/rf5c396l/RB5C396/rf5c396 36 index : 07h default value : 0000 0000b read & write bit7 : i/o window 1 waite state. if this bit is set to ??or this wait state is set by the wait# signal which is common to 8 and 16bit, 16bit system accesses occur with 1 additional wait state(4 sysclk). bit6 : i/o window 1 zero waite state. if this bit is set to ?? 8bit system i/o accesses occur with zero additional wait states and zerows# signal will be active. bit5 : i/o window 1 iocs16# source. if this bit is set to ?? iocs16# signal will be generated based on the value of the data size bit. if this bit is set to ?? iocs16# signal will be generated based on the iois16# signal. bit4 : i/o window 1 data size. ??indicates 8bit mode, and ??indicates 16bit mode. bit3 : i/o window 0 wait state. if this bit is set to ??or this wait state is set by the wait # signal which is common to 8 and 16bit, 16bit system accesses occur with 1 additional wait state(4 sysclk). bit2 : i/o window 0 zero waite state. if this bit is set to ?? 8bit system i/o accesses occur with zero additional wait states and zerows# signal will be active. bit1 : i/o window 0 iocs16# source. if this bit is set to ?? iocs16# signal will be generated based on the value of the data size bit. if this bit is set to ?? iocs16# signal will be generated based on the iois16# signal. bit0 : i/o window 0 data size. ??indicates 8bit mode, and ??indicates 16bit mode. index i/o window 0 : 08h default value : 0000 0000b read & write index i/o window 1 : 0ch i/o window 0 start address a7 to a0 bit7 : address 7 bit6 : address 6 bit5 : address 5 bit4 : address 4 bit3 : address 3 bit2 : address 2 bit1 : address 1 bit0 : address 0 2. i/o mapping 2.2 i/o ad dress n star t register lo w byte 2.1 i/o contr ol register
rf5c296/rf5c396l/RB5C396/rf5c396 37 index i/o window 0 : 09h default value : 0000 0000b read & write index i/o window 1 : 0dh i/o window 0 start address a15 to a8 bit7 : address 15 bit6 : address 14 bit5 : address 13 bit4 : address 12 bit3 : address 11 bit2 : address 10 bit1 : address 9 bit0 : address 8 index i/o window 0 : 0ah default value : 0000 0000b read & write index i/o window 1 : 0eh i/o window 0 stop address a7 to a0 bit7 : address 7 bit6 : address 6 bit5 : address 5 bit4 : address 4 bit3 : address 3 bit2 : address 2 bit1 : address 1 bit0 : address 0 index i/o window 0 : 0bh default value : 0000 0000b read & write index i/o window 1 : 0fh i/o window 0 stop address a15 to a8 bit7 : address 15 bit6 : address 14 bit5 : address 13 bit4 : address 12 bit3 : address 11 bit2 : address 10 bit1 : address 9 bit0 : address 8 2.5 i/o ad dress n stop register high byte 2.4 i/o ad dress n stop register lo w byte 2.3 i/o ad dress n star t register high byte
rf5c296/rf5c396l/RB5C396/rf5c396 38 index : memory window 0 10h memory window 1 18h memory window 2 20h memory window 3 28h memory window 4 30h default value : 0000 0000b read & write bit7 : address 19 bit6 : address 18 bit5 : address 17 bit4 : address 16 bit3 : address 15 bit2 : address 14 bit1 : address 13 bit0 : address 12 index : memory window 0 11h memory window 1 19h memory window 2 21h memory window 3 29h memory window 4 31h default value : 0000 0000b read & write bit7 : data size bit. ??indicates 8bit mode and ??indicates 16bit mode. bit6 : zero wait state. if this bit is set to ?? an 8bit system memory access occur with zero additional wait states and zerows# signal will be active. the wait# signal will override this bit. bit5 : scratch bit (unused but intended for reading and writing.) bit4 : scratch bit (unused but intended for reading and writing.) bit3 : address 23 bit2 : address 22 bit1 : address 21 bit0 : address 20 3. memor y mapping 3.2 system memor y ad dress n mapping star t high byte register inde x 3.1 system memor y ad dress n mapping star t lo w byte register inde x
rf5c296/rf5c396l/RB5C396/rf5c396 39 index : memory window 0 12h memory window 1 1ah memory window 2 22h memory window 3 2ah memory window 4 32h default value : 0000 0000b read & write bit7 : address 19 bit6 : address 18 bit5 : address 17 bit4 : address 16 bit3 : address 15 bit2 : address 14 bit1 : address 13 bit0 : address 12 index : memory window 0 13h memory window 1 1bh memory window 2 23h memory window 3 2bh memory window 4 33h default value : 0000 0000b read & write bit7 : wait state bit 1 bit6 : wait state bit 0 bit5 : reserved bit4 : reserved bit3 : address 23 bit2 : address 22 bit1 : address 21 bit0 : address 20 wait state bit 1 wait state bit 0 # of additional cycle # of sysclk per access 0 0 standard 16bit cycle 3 0 1 1 4 1 0 2 5 1 1 3 6 3.4 system memor y ad dress n mapping stop high byte register 3.3 system memor y ad dress n mapping stop lo w byte register
rf5c296/rf5c396l/RB5C396/rf5c396 40 index : memory window 0 14h memory window 1 1ch memory window 2 24h memory window 3 2ch memory window 4 34h default value : 0000 0000b read & write bit7 : offset address 19 bit6 : offset address 18 bit5 : offset address 17 bit4 : offset address 16 bit3 : offset address 15 bit2 : offset address 14 bit1 : offset address 13 bit0 : offset address 12 index : memory window 0 15h memory window 1 1dh memory window 2 25h memory window 3 2dh memory window 4 35h default value : 0000 0000b read & write bit7 : write protect bit. if this bit is set t o ?? write operations to the pc card through the corresponding system memory window are inhibited. bit6 : reg active.if this bit is set to ?? accesses to the system memory window will result in attribute memory on pc card being accessed. bit5 : offset address 25 bit4 : offset address 24 bit3 : offset address 23 bit2 : offset address 22 bit1 : offset address 21 bit0 : offset address 20 3.6 car d memor y offset ad dress n high byte register 3.5 car d memor y offset ad dress n lo w byte register
rf5c296/rf5c396l/RB5C396/rf5c396 41 index : 1fh default value : 0000 0000b read & write bit7 : when set to ?? this bit specifies disabling bit7 in the data bus for an i/o address of 377h or 3f7h (at read time). when set to ?? this bit specifies no such disabling. this bit defaults to ??and can be set indepen - dently of bit0. bit6 : in pcmcia-ata mode, the value of this bit appears at ca25. bit5 : in pcmcia-ata mode, the value of this bit appears at ca24. bit4 : in pcmcia-ata mode, the value of this bit appears at ca23. bit3 : in pcmcia-ata mode, the value of this bit appears at ca22. bit2 : in pcmcia-ata mode, the value of this bit appears at ca21. bit1 : in pcmcia-ata mode, if this bit is set to ?? the spkr# input works as an led input and irq12 works as an open drain led output. default value is ?? bit0 : pcmcia-ata mode bit. ??selects pcmcia-ata mode and ??selects pcmcia mode. default value is ?? index : 2fh default value : 0000 0000b read & write bit7 to bit6 : dma request selection bits. dreq from pc card is defined according to these 2 bits. default values are ?? bit5 : if this bit is set to ?? dreq is ??active. if this bit is set to ?? dreq is ??active. default value is ?? bit4 : dma mode tc selection bit. if this bit is set to ?? irq11 works as tc. if this bit is set to ? , irq15 works as tc. bit3 : direct 5v/3.3v switch enable. if bit4 of power and resetdrv control register is set to ? , setting this bit to ??will allow the status of 5vdet/gpi pin to select vcc3en# or vcc5en# independently of bit0. default value is ?? bit2 : input acknowledge enable. if this bit is set to ?? inpack# pin function is enabled. if this bit is set to ?? inpack# is disabled. when the input inpack# pin signal is active, i/o read data are output to the system data bus only if the input inpack# pin signal is held at ?? default value is ?? bit1 : ireq# sense selection bit. if this bit is set to ?? ireq# is ??ctive. if this bit is set to ? , ireq# is ??ctive. default value is ?? bit0 : voltage selection bit. if bit4 of power and resetdrv control register is set to ?? setting this bit to ??will set vcc3en# ?? if bit4 of power and resetdrv control register setting this bit to ??will set vcc5en# ?? default value is ?? bit 7 bit 6 dreq 01 inpack# 10 spkr#/led# 11 iois16# 4. expansion function 4.2 mode contr ol register 2 4.1 mode contr ol register 1
rf5c296/rf5c396l/RB5C396/rf5c396 42 index : 36h default value : 0000 0000b read & write bit7 : offset address 7 bit6 : offset address 6 bit5 : offset address 5 bit4 : offset address 4 bit3 : offset address 3 bit2 : offset address 2 bit1 : offset address 1 bit0 : always ? this function is available only in rf5c396. i/o offset address can be set in the following registers. card i/o address is the summation result of system address and i/o offset address. index : 37h default value : 0000 0000b read & write bit7 : offset address 15 bit6 : offset address 14 bit5 : offset address 13 bit4 : offset address 12 bit3 : offset address 11 bit2 : offset address 10 bit1 : offset address 9 bit0 : offset address 8 index : 38h default value : 0000 0000b read & write bit7 : offset address 7 bit6 : offset address 6 bit5 : offset address 5 bit4 : offset address 4 bit3 : offset address 3 bit2 : offset address 2 bit1 : offset address 1 bit0 : always ? 5. i/o ad dress remapping 5.3 car d i/o offset ad dress 1 lo w byte register 5.2 car d i/o offset ad dress 0 high byte register 5.1 car d i/o offset ad dress 0 lo w byte register
rf5c296/rf5c396l/RB5C396/rf5c396 43 index : 39h default value : 0000 0000b read & write bit7 : offset address 15 bit6 : offset address 14 bit5 : offset address 13 bit4 : offset address 12 bit3 : offset address 11 bit2 : offset address 10 bit1 : offset address 9 bit0 : offset address 8 index : 3ah default value : 32h (rf5c296), b2h (rf5c396) read only read only register, 32h is read back from rf5c296, b2h is read back from rf5c396. index : 3bh default value : 0000 0000b read & write bit 7 t o bit2 : reserved. bit 1 : dma mode enable bit. when this bit is set to ?? the dma mode is selected in which dma-related signals are redefined as described in ?ma mode? this bit defaults to ? . this bit cannot be set to ??simultaneously for slot #0 and slot #1. bit0 : pcmcia interface disable bit. if this bit is set to ?? signals shown in the below table are set to ?? all pcmcia interface signals are disabled and become ?? the built-in pull-down resistor is disabled for data bus signals. slot output sig - nals will be caused to transition to high impedance even when bit 0 is set in the power and resetdrv control register. input output cd1#, cd2#, bvd1, bvd2, rdy/bsy#, wait#, wp, inpack# ca[25 : 0], cd[15 : 0], ce1#, ce2#, ciord#, ciowr#, oe#, reg#, reset, we# 5.6 mode contr ol register 3 5.5 chip identification register (read onl y) 5.4 car d i/o offset ad dress 1 high byte register
rf5c296/rf5c396l/RB5C396/rf5c396 44 slo t #0 offset slo t #1 offset register name identification and revision interface status power and resetdrv control interrupt and general control card status change card status change interrupt configuration address window enable i/o control i/o address 0 start low byte i/o address 0 start high byte i/o address 0 stop low byte i/o address 0 stop high byte i/o address 1 start low byte i/o address 1 start high byte i/o address 1 stop low byte i/o address 1 stop high byte system memory address 0 mapping start low byte system memory address 0 mapping start high byte system memory address 0 mapping stop low byte system memory address 0 mapping stop high byte card memory offset address 0 low byte card memory offset address 0 high byte card detect and general control reserved system memory address 1 mapping start low byte system memory address 1 mapping start high byte system memory address 1 mapping stop low byte system memory address 1 mapping stop high byte card memory offset address 1 low byte card memory offset address 1 high byte global control 1 0 0 0 0 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 default value 7654 to 3210 6. summar y of internal register +00h +01h +02h +03h +04h +05h +06h +07h +08h +09h +0ah +0bh +0ch +0dh +0eh +0fh +10h +11h +12h +13h +14h +15h +16h +17h +18h +19h +1ah +1bh +1ch +1dh +1eh +40h +41h +42h +43h +44h +45h +46h +47h +48h +49h +4ah +4bh +4ch +4dh +4eh +4fh +50h +51h +52h +53h +54h +55h +56h +57h +58h +59h +5ah +5bh +5ch +5dh +5eh
rf5c296/rf5c396l/RB5C396/rf5c396 45 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0* 0 0 0 0 0 0 0 0 mode control 1 system memory address 2 mapping start low byte system memory address 2 mapping start high byte system memory address 2 mapping stop low byte system memory address 2 mapping stop high byte card memory offset address 2 low byte card memory offset address 2 high byte reserved reserved system memory address 3 mapping start low byte system memory address 3 mapping start high byte system memory address 3 mapping stop low byte system memory address 3 mapping stop high byte card memory offset address 3 low byte card memory offset address 3 high byte reserved mode control 2 system memory address 4 mapping start low byte system memory address 4 mapping start high byte system memory address 4 mapping stop low byte system memory address 4 mapping stop high byte card memory offset address 4 low byte card memory offset address 4 high byte card i/o offset address 0 low byte card i/o offset address 0 high byte card i/o offset address 1 low byte card i/o offset address 1 high byte chip identification mode control 3 slo t #0 offset slo t #1 offset register name default value 7654 to 3210 +1fh +20h +21h +22h +23h +24h +25h +26h +27h +28h +29h +2ah +2bh +2ch +2dh +2eh +2fh +30h +31h +32h +33h +34h +35h +36h +37h +38h +39h +3ah +3bh +5fh +60h +61h +62h +63h +64h +65h +66h +67h +68h +69h +6ah +6bh +6ch +6dh +6eh +6fh +70h +71h +72h +73h +74h +75h +76h +77h +78h +79h +7ah +7bh * ) chip identification register bit7 is read back ??from rf5c296, ??from rf5c396.
rf5c296/rf5c396l/RB5C396/rf5c396 46 hard w are design considera tions for the rf5c296 and the rf5c396, the spkrout#, ri_out#, and intr# pins function as output pins normally but as input pins whose input status determine internal settings during the time that the resetdrv pin is held at high level as shown in the diagram below. internal settings can be made by pulling up or down these pins to such a degree as not to affect normal operation (on the order of 10k ? for ordinary circuits). the spkrout# and ri_out# pins determine an index range for access to the internal registers as shown in the table below : ri_out# vdd vdd gnd gnd spkrout# vdd gnd vdd gnd device bit 0 0 1 1 slot bit 0 1 0 1 index range 00 to 3fh 40 to 7fh 80 to bfh c0 to efh ?rf5c396 spkrout# vdd vdd gnd gnd device bit 0 0 1 1 slot bit 0 1 0 1 index range 00 to 3fh 40 to 7fh 80 to bfh c0 to efh s p k r o u t # r i _ o u t # i n t r # r e s e t d r v f u n c t i o n a s i n p u t p i n s f u n c t i o n a s o u t p u t p i n s p i n s t a t u s c a p t u r i n g 1. initial v alue setting pins ?rf5c296 1.1 spkr out# and ri_out# pins
rf5c296/rf5c396l/RB5C396/rf5c396 47 1.2 intr# pin the intr# pin determines whether to use external decoding or internal decoding for access to the internal reg - isters. pulling up and down the intr# pin specifies internal decoding and external decoding, respectively. for details, see ?. access to internal registers?in ?unctional description? basically, connections to the isa bus only require connections to corresponding bus pins. the iocs16#, memcs16#, zerows#, and iochrdy pins are open-drain output pins which require an external pull-up resistor in the absence of any pull-up resistor provided on the isa bus. these resistors are designed to drive a 300 ? pull-up resistor (for the iocs16#, memcs16#, and zerows# pins) and a 1k ? pull-up resistor (for the iochrdy). the zerows# and iochrdy pins are also caused to transition to ??level for the maximum duration of one clock pulse upon transition from low level to high impedance as shown in the figure below. originally, strict regula - tion of the pull-up resistor for these open-drain output pins is required for the fast rising edge of their pin signals but not recommended in consideration of current consumption. for the rf5c296 and the rf5c396, such unique designs of the zerows# and iochrdy pins allow restriction of current consumption without strict regulation of the pull-up resistor to such a degree as not to affect any other system. the cs# pin is intended to determine an i/o address for access to the control registers for the rf5c296 and the rf5c396 and not directly related to access to the card windows. as described before, either external decoding or internal decoding can be used to determine an i/o address for access to the control registers. (for details, see ?. access to internal registers?in ?unctional descrip - tion?) when external decoding is used, an i/o address for access to the control registers can be determined by decod - ing the address signals output from the sa15 to the sa1 (or the sa23 to the sa16 for some systems) for input with negative logic to the cs# pin. when internal decoding is used, access to the internal registers is conditional upon the cs# pin held at ??and an i/o address of 03e0h or 03e1h. in this case, the cs# pin must receive a signal input which becomes active only when the sa15 to sa10 pins are all caused to transition to ?? this is because the status of the ce# pin affects the power down mode (specified by bit0 in the global control register (index : 1eh)). when the power down mode is not in use, therefore, the ce# pin should be held at ?? i o c h r d y o n e c l o c k p u l s e t 2 1 z e r o w s # s y s c l k 2. connections to system bus 2.2 cs# pin 2.1 iocs16#, memcs16#, zer o ws#, and iochrd y pins
rf5c296/rf5c396l/RB5C396/rf5c396 48 for the rf5c296 and the rf5c396, reset operation is conditional upon the powergood pin held at ??nd the resetdrv pin held at ?? when not in use, therefore, the powergood pin should be held at ?? 2.4 irq12 pin and led v c c i r q 1 2 besides connection to the isa bus, the irq12 pin is available in connection to the led in the pcmcia_ata mode. direct connection to the led causes so large a current load to the irq12 pin that it should be connected in series to a limiting resistor on the order of 300 ? to 1k ? for connection to the vcc as shown in the figure below. the limiting resistor should be regulated in such a manner that current flowing into the ic core does not exceed 20 ma. whether external decoding or internal decoding is used, note that an address for access to the i/o window (not an address to access to the internal registers) is determined by decoding the address signals output from the sa23 to sa16 pins to (0000 0000)b. 2.3 resetdr v and po wergood pins
notes for connecting to system bus except isa bus rf5c296/rf5c396l/RB5C396/rf5c396 49 the rf5c296 and the rf5c396 must be connected to any other system bus than the isa bus in consideration of the fol - lowing pins: 1) bale pin the bale pin signal is intended to latch the address signals output from the la23 to la17 pins because retention of these pin signals is not guaranteed in the entire instruction cycle on the isa bus. in practice,they are half-latched. the bale pin may be held at h , therefore, when the la23 to la17 pin signals are retained in the entire instruction cycle on any other bus in the same manner as the sa16 to sa0 2) aen pin the aen pin signal indicates the dma mode when held at h . as such, it should be held at ? when the dma mode is not in use. 3) refresh# pin the refresh# pin signal indicates the refresh period of the isa bus when held at ? ? for the rf5c296 and the rf5c396, memory access is conditional upon the refresh# pin signal held at h . the refresh# pin signal should be held at h , therefore, when not in use. 4) sysclk pin the sysclk pin signal normally has a frequency of 8.33mhz on the isa bus. for the rf5c296 and the rf5c396, the sysclk pin signal is used for the following five purposes : ?determination of wait time ?determination of the pulse width of the intr# pin signal ?determination of the reset pulse width of the card states change register in the explicit write back mode. ?bit 0 function of card detect and general control register. ? determination of the high-level duration of the zerows# and iochrdy pin signals (for details, see ?.1 iocs16#, memcs16#, zerows#, and iochrdy pins?in ?. connections to system bus?) as long as the above purposes can be achieved, the sysclk pin signal may be available at a maximum frequency of 11mhz or in dc form.
rf5c296/rf5c396l/RB5C396/rf5c396 50 power supply to which pins are pulled up (vcc common to card power supply) vcc_at pins which must be pulled up rdy/bsy#,inpack#,wait#, wp,bvd1,bvd2 cd1#,cd2#,vs1# the personal computer memory card industry association (pcmcia) standard requires that some types of pins should be pulled up on the pc card slots. besides these pins,there are some pins which must be pulled up on the system side. they are listed in the table below. for the rf5c296 and the rf5c396, the vsi# pin, which is connected to the 5vdet/gpi pin internally pulled up, requires no external pull-up resistor while the other pins listed above require an external pull-up resistor. for details, see ?.2 5vdet/gpi and vsi# pins? basically, the cd1# and cd2# pins should be pulled by a power supply which survives after removal of the pc card from the pc card slot and therefore be confined to the vcc_core or the vcc_at. for the rf5c296 and the rf5c396, in particular, the cd1# and cd2# pins are powered by, and should therefore be pulled up to, the vcc_at. originally, the 5vdet/gpi pin is used as a general-purpose input (gpi) pin capable of generating interrupts upon occurrence of any input change. the vs1# pin is connected to the gnd pin on the 3.3v pc card and no con - nection pin on any other card. the 5vdet/gpi pin, which is internally pulled up as described before, can be con - nected to the vs1# pin as shown in the figure below to identify whether the pc card supply voltage is 5 or 3.3v. the 5vdet/gpi pin must be connected to the vs1# pin in consideration of the following : ?an inverted signal from the 5vdet/gpi pin is read back to bit7 in the interface status register. ?bit2 (gpi enable bit) must always be set to ??in the card detect and control register. for details on bit7 in the interface status register and bit2 (gpi enable bit) in the card detect and control register, see ?. access to internal registers?in ?unctional description? v c c 3 e n # v c c 5 e n # v c c s l o t # 5 v d e t / g p i r f 5 c 2 9 6 / r f 5 c 3 9 6 p o w e r c o n t r o l c i r c u i t s p c m c i a c a r d s l o t v c c v s 1 # 3. connections to pcmcia slot 3.2 5vdet/gpi and vs1# pins 3.1 pull-up resistor
rf5c296/rf5c396l/RB5C396/rf5c396 51 the rf5c296 and the rf5c396 are designed to supply separate power for the ic core, the isa bus interface, and the pc card slots from the vcc_core, the vcc_at, and the vcc_slot, respectively, as shown in the figure below : available power supply combinations are shown in the table below : 5v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 5v 5v 3.3v 5v 3.3v 5v 5v 3.3v 3.3v 5v 5v 5v 3.3v 3.3v 5v 3.3v 5v 3.3v 5v 5v 5v 5v 5v 3.3v 3.3v 3.3v 3.3v as is clear from the above table, the 5v power supply for the ic core (the vcc_core) is available in combina - tion with only the 5v peripheral power supplies (the vcc_slot#0 for the card slot#0, the vcc_slot#1 for the card slot#1, and the vcc_at for the isa bus interface). on the contrary, the 3.3v power supply for the ic core is available in combination with both the 3.3v and 5v peripheral power supplies. i s a b u s v c c _ a t v c c _ c o r e v c c _ s l o t # 0 s l o t # 0 s l o t # 0 i n t e r f a c e s l o t # 1 i n t e r f a c e s l o t # 1 v c c _ s l o t # 1 c o r e l o g i c i s a b u s i n t e r f a c e r f 5 c 2 9 6 / r f 5 c 3 9 6 4. connections to p o wer suppl y system core (vcc_core) card slot#0 (vcc_slot#0) card slot#1 (vcc_slot#1) isa bus interface (vcc_at) 4.1 vcc_core, vcc_slo t , and vcc_a t
rf5c296/rf5c396l/RB5C396/rf5c396 52 the rf5c296 and the rf5c396 are designed to have their power supply system controlled by four output pins : vcc3en#, vcc5en#, vpp_en0, and vpp_en1. set the vcc3en# pin to ??by controlling the internal register in case of that the 3.3v is supplied to the power supply (vcc_slot) of the pc card slots. set the vcc5en# pin to ? by controlling the internal register in case of that the 5.0v is supplied to the power supply (vcc_slot) of the pc card slots. both the vcc3en# and vcc5en# cannot be set to ??simultaneously. set the vpp_en0 pin to ??by controlling the internal register in case of that the vpp (5v) is supplied to the vpp of the pc card slots. set the vpp_en1 pin to ??by controlling the internal register in case of that the vpp (12v) is supplied to the vpp of the pc card slots. both the vpp_en0 and vpp_en1 pins may be set to ??simulta - neously under certain register settings, thus requiring due attention in either hardware or software design. the intel 82365sl has the four vpp_en pins and provides separate control over the two power supply pins (vpp1 and vpp2). on the contrary, the rf5c296 and the rf5c396 have the two vpp_en pins and provide simulta - neous control over the vpp1 and vpp2 pins. as an alternative measure, the rf5c296 and the rf5c396 allow separate control over the vpp1 and vpp2 pins by the vpp_en0 and vpp_en1 pins, respectively, provided that both the vpp1 and vpp2 must be provided with either the 5v or 12v power supply without fail. these four output pins are controlled by the power and resetdrv control register (index : 02h) and the mixed voltage control register (index : 2fh). these pins can be used to configure an external driver for applying voltage to the two power supply pins (vpp1 and vpp2) on the pc card slots. power supply circuitry for the rf5c296 and the rf5c396 is exemplified in the dia - grams below : 1 2 v v p p _ e n 1 p c c a r d v p p v p p _ e n 0 p c c a r d v c c 5 v 3 . 3 v v c c 3 e n # p c c a r d v c c 5 v v c c 5 e n #
rf5c296/rf5c396l/RB5C396/rf5c396 53 to connect multiple units of the rf5c296 or the rf5c396 to the same system bus, their respective pc card slots must be provided with independent indexes by connecting a pull-up or pull-down resistor to the spkrout# and ri_out# pins. (for details, see ?. plural slot system?in ?unctional description?and ?. initial value setting pins?in ?ardware design considerations? multiple connections to the system bus are wired or using the irqn pins. the irqn pins should be used in consideration of a conflict between interrupt request signals. driving software for ordinary pc card controllers assigns the same irq number to different interrupt signals derived from the pc card status change. such assign - ment causes a conflict between interrupt request signals. this problem can be solved by the following three mea - sures : (1) confining irqn interrupt request signals derived from the pc card status change to any one unit of the rf5c296 or the rf5c396 and applying polling to the other units at the sacrifice of increased overall current con - sumption resulting from constant system operation. (2) re-designing driver software to assign different irqn pins to interrupt request signals derived from the pc card status change for each ic core at the sacrifice of additional recourse to the irqn pins which are originally deficient as resources. (3) connecting the irqn pins as shown in the diagram below at the sacrifice of additional hardware installation. basically, the irqn pins for assigning the same irq number to interrupt request signals derived from the pc card status change would be sufficient to implement the hardware configuration shown in the diagram below. in any ordinary system, however, the same irq number cannot always be assigned to interrupt request signals derived from the pc card status change, resulting in many cases where circuit change cannot be confined to the single irqn pin. i r q n 1 i r q n 2 p u l l - d o w n r e s i s t o r o n s y s t e m s i d e i r q n notice under the supply voltage of 3.3v, diode selection requires sufficient care to regulate a voltage drop to a small value. 5. connecting multiple units of rf5c296 or rf5c396
rf5c296/rf5c396l/RB5C396/rf5c396 54 softw are design considera tions the rf5c296 and the rf5c396 contains about fifty 8bit internal registers. one of these internal registers, the identification and revision register (index : 00h), which is intended for only reading operation and fixed at 83h, is useful for confirming access to the other internal registers. one of the initial requirements in inserting the pc card is to identify whether it is the i/o card or the memory card. such pc card types can be identified by bit5 in the interrupt and general control register (index : 03h). this bit indicates the i/0 card and the memory card when set to ??and ??, respectively. the rf5c296 and the rf5c396 are designed to interface between the cpu bus, such as the isa bus, and the pc card bus. unlike ordinary ics, therefore, these ics provides address mapping mainly to establish a correspondence between the cpu bus and the pc card bus. in view of such differences, therefore, this section provides separate description of ?/o address mapping?and ?emory address mapping? 2. identification of pc car d t ypes 3. ad dress mapping and ad dress windo w setting the i/o address space occupies 64kb ranging from ?000h?to ?ffffh?on the isa bus. similarly, the i/o address space occupies 64kb ranging from ?000h?to ?ffffh?on the pc card bus, too. the rf5c296 is capable of mapping any given two i/o address windows (ranges) on the isa bus to the i/o address windows on the pc card bus in units of 1 bytes for each pc card slot in such a manner as to ensure address matching between the isa bus and the pc card bus. an i/o address window can be set by setting the low-order 8bits of its starting address in the i/o address n start low byte register (index : 08h (i/o window 0) and 0ch (i/o window 1)) and the high-order 8bits in the i/o address n start high byte register (index : 09h (i/o window 0) and 0dh (i/o window 1)) while setting the low- order 8bits of its ending address in the i/o address n stop low byte register (index : 0ah (i/o window 0) and 0eh (i/o window 1)) and the high-order 8bits in the i/o address n stop high byte register (index : 0bh (i/o window 0) and 0fh (i/o window 1)). 1. confirmation of access to internal register s 3.1 i/o ad dress space
rf5c296/rf5c396l/RB5C396/rf5c396 55 the rf5c296 provides i/o address mapping as shown in the figure below : in the above figure, addresses ?3e0h?and ?3e1h?form an internal address space for use in internal decoding. on the other hand, the rf5c396 is capable of i/o address mapping in such a manner as to ensure i/o address mismatching between the isa bus and the pc card bus. the above-described settings of the i/o address n start/stop low/high byte registers for the rf5c296 can be added to the settings of the card i/o offset address n low/high byte registers (index : 36h (low-byte window 0), 37h (high-byte window 0), 38h (low-byte window 1), and 39h (high-byte window 1)) to form two's complement numbers representing i/o addresses on the pc card bus. the card i/o offset address n low/high byte registers, which always default to ?0h? may be omitted from setting to ensure i/o address matching between the isa bus and the pc card bus in the same manner as for the rf5c296. i / o a d d r e s s o n i s a b u s i / o a d d r e s s o n p c c a r d b u s 0 0 0 0 h i / o w i n d o w 0 i / o w i n d o w 1 a a a a h b b b b h 0 3 e 0 h 0 3 e 1 h c c c c h d d d d h f f f f h i / o a d d r e s s w i n d o w f o r a c c e s s t o i n t e r n a l r e g i s t e r s ( 0 3 e 0 h a n d 0 3 e 1 h ) ( f o r u s e i n i n t e r n a l d e c o d i n g ) 0 0 0 0 h a a a a h b b b b h c c c c h d d d d h f f f f h ?i/o address mapping by rf5c296
rf5c296/rf5c396l/RB5C396/rf5c396 56 the rf5c396 provides i/o address mapping as shown in the figure below : the settings of the internal registers relating to i/o address window setting are shown in the table on the next page. for details on the individual internal registers, see ?nternal registers? i / o a d d r e s s w i n d o w f o r a c c e s s t o i n t e r n a l r e g i s t e r s ( 0 3 e 0 h a n d 0 3 e 1 h ) ( f o r u s e i n i n t e r n a l d e c o d i n g ) i / o a d d r e s s o n p c c a r d b u s i / o a d d r e s s o n i s a b u s ( c c c c + f f f f ) h ( d d d d + f f f f ) h ( a a a a + e e e e ) h ( b b b b + e e e e ) h f f f f h i / o w i n d o w 0 i / o w i n d o w 1 0 0 0 0 h a a a a h b b b b h 0 3 e 0 h 0 3 e 1 h c c c c h d d d d h f f f f h 0 0 0 0 h ?i/o address mapping by rf5c296
rf5c296/rf5c396l/RB5C396/rf5c396 57 06h : bit6 06h : bit7 07h : bit1 07h : bit5 index index index index index index index index 07h : bit3 07h : bit7 0bh : bit7 to 0 0fh : bit7 to 0 0ah : bit7 to 0 0eh : bit7 to 0 37h : bit7 to 0 39h : bit7 to 0 36h : bit7 to 0 38h : bit7 to 0 the memory address space occupies 16mb ranging from ?00000h?to ?ffffffh?on the isa bus. on the con - trary, the memory address space occupies 64mb ranging from ?000000h?to ?ffffffh?on the pc card bus. the rf5c296 and the rf5c396 are capable of mapping any given five memory address windows (ranges) on the isa bus to the memory address windows on the pc card bus in units of 4kb for each pc card slot. on the isa bus, each memory address window ranges from the starting address specified by the system memory address n mapping start high/low byte registers to the ending address specified by the system memory address n mapping stop high/low byte registers. on the pc card bus, each memory address window equals to its equiva - lent on the isa bus plus the setting of the card memory offset address n low byte register (forming a two's com - plement number). ?i/o address window setting start address stop address off set address (only rf5c396) wait state zero wait state data size iocs16# source enable window 0 window 1 09h : bit7 to 0 0dh : bit7 to 0 08h : bit7 to 0 0ch : bit7 to 0 07h : bit2 07h : bit6 07h : bit0 07h : bit4 these bits can be used to specify the ending address of the applicable i/o address window. these bits can be used to specify the offset address of the applicable i/o address window. these bits can be used to specify the one wait state (4sysclk) 16bit i/o cycle and the stan - dard 16bit i/o cycle when set to ??and ?? respectively. the 16bit i/o cycle is unavailable in zero wait state form. these bits can be used to specify the zero wait state 8bit i/o cycle rendering the zerows# pin signal active and the standard 8bit i/o cycle when set to ??and ?? respectively. these bits can be used to specify the 8bit mode and the 16bit mode when set to ??and ?? respectively. these bits can be used to specify the dependence of the iocs16# pin signal on the iois16# pin signal from the pc card and on the data size bit when set to ??and ?? respectively. these bits can be used to specify rendering the applicable i/o window active when set to ?? these bits can be used to specify the starting address of the applicable i/o address window.
rf5c296/rf5c396l/RB5C396/rf5c396 58 particularly, on the pc card bus, there are two types of memory available : the common memory and the attribute memory, which can be selected by the card memory offset address n high/low byte registers. the common memory and the attribute memory are used mainly for ordinary access and for storage of such data as pc card information, respectively. during access to the attribute memory, the reg# pin signal is held at ?? the rf5c296 and rf5c396 provide memory address mapping as shown in the figure below : in the above figure, addresses ?aaa000)h?and ?ccc000)h?can be set in the system memory address n mapping start high/low byte registers, addresses ?bbbfff)h?and ?dddfff)h?in the system memory address n mapping stop high/low byte registers, and addresses ?pppp000)h?and ?qqqq000)h?in the card memory offset address n high/low byte registers. m e m o r y a d d r e s s e s o n i s a b u s m e m o r y a d d r e s s e s ( i n c o m m o n m e m o r y ) o n p c c a r d b u s m e m o r y a d d r e s s e s ( i n a t t r i b u t e m e m o r y ) o n p c c a r d b u s 0 0 0 0 0 0 h ( a a a 0 0 0 ) h ( b b b f f f ) h ( c c c 0 0 0 ) h ( d d d f f f ) h f f f f f f h m e m o r y w i n d o w 0 m e m o r y w i n d o w n 1 6 m b m e m o r y a d d r e s s s p a c e 0 0 0 0 0 0 h + ( c c c 0 0 0 ) h o r o r ( p p p p 0 0 0 ) h 3 f f f f f f h + ( b b b f f f ) h + ( a a a 0 0 0 ) h ( p p p p 0 0 0 ) h + ( d d d 0 0 0 ) h ( q q q q 0 0 0 ) h ( q q q q 0 0 0 ) h
rf5c296/rf5c396l/RB5C396/rf5c396 59 31h : bit3 to 0 30h : bit7 to 0 33h : bit3 to 0 32h : bit7 to 0 35h : bit5 to 0 34h : bit7 to 0 31h : bit6 31h : bit7 33h : bit7 to 6 35h : bit7 35h : bit6 29h : bit3 to 0 28h : bit7 to 0 2bh : bit3 to 0 2ah : bit7 to 0 2dh : bit5 to 0 2ch : bit7 to 0 29h : bit6 29h : bit7 2bh : bit7 to 6 2dh : bit7 2dh : bit6 21h : bit3 to 0 20h : bit7 to 0 23h : bit3 to 0 22h : bit7 to 0 25h : bit5 to 0 24h : bit7 to 0 21h : bit6 21h : bit7 23h : bit7 to 6 25h : bit7 25h : bit6 19h : bit3 to 0 18h : bit7 to 0 1bh : bit3 to 0 1ah : bit7 to 0 1dh : bit5 to 0 1ch : bit7 to 0 19h : bit6 19h : bit7 1bh : bit7 to 6 1dh : bit7 1dh : bit6 11h : bit3 to 0 10h : bit7 to 0 13h : bit3 to 0 12h : bit7 to 0 15h : bit5 to 0 14h : bit7 to 0 11h : bit6 11h : bit7 13h : bit7 to 6 15h : bit7 15h : bit6 index index index index index index index index window 0 window 1 window 2 window 3 window 4 start address stop address offset address zero wait state data size wait state write protect reg active the settings of the internal registers relating to memory address window setting are shown in the table below. for details on the individual internal registers, see ?nternal registers? these bits can be used to specify the starting address of the applicable memory address window. (a23 to a12) these bits can be used to specify the ending address of the applicable memory address window. (a23 to a12) these bits can be used to specify the offset address of the applicable memory address window. (a25 to a12) these bits can be used to specify zero wait state access when set to ??in the 8bit mode, giving first priori - ty to the wait# pin signal from the pc card. these bits can be used to specify 8bit access and 16bit access when set to ??and ?? respectively. these bits can be used to specify memory access cycles, giving first priority to the wait# pin signal from the pc card. these bits can be used to specify write protection on memory. these bits can be used to specify access to the attribute memory in the ic card when set to ?? bit7 bit6 # of additional cycle # of sysclk per access 0 0 1 1 0 1 0 1 1 2 3 standard 16bit cycle (additional cycle is ??) 3 4 5 6 ?memory address window setting
rf5c296/rf5c396l/RB5C396/rf5c396 60 window 0 window 1 window 2 window 3 window 4 this bit can be used to specify the generation of the memcs16# pin signal through decoding the a23 to a17 pin signals and through decoding the a23 to a12 pin signals when set to ??and ?? respectively. these bits can be used to specify rendering the applicable memory address window active when set to ?? memcs16# window enable index index 06h : bit0 06h : bit1 06h : bit2 06h : bit3 06h : bit4 06h : bit5
s y s c l k m e m r # m e m w # z e r o w s # i o c h r d y s y s c l k m e m r # m e m w # z e r o w s # i o c h r d y s y s c l k m e m r # m e m w # z e r o w s # i o c h r d y t s t c t s t c 1 t s t c t s t s t c t s t c 1 t c 1 rf5c296/rf5c396l/RB5C396/rf5c396 61 to enhance understanding of memory access cycles, three types of 16bit memory access cycles are shown in the timing charts below : (1) standard cycle (3 sysclk cycle) (2) zero wait state cycle (2 sysclk cycle) (3) one wait state cycle (4 sysclk cycle)
rf5c296/rf5c396l/RB5C396/rf5c396 62 a two or three wait state memory access cycle can be implemented by adding the tc1 in the one wait state mem - ory access cycle of (3). the 16bit memory access cycle is identical to the 16bit i/o cycle in terms of the output tim - ing for the iochrdy pin signal except that the latter is unavailable in zero wait state form. the rf5c296 and the rf5c396 generate interrupts derived from the following sources : for i/o card : interrupts derived from the ireq# pin status change : pc card status change : cd1# and/or cd2# pin status change stschg# pin status change (when bit7 is set interrupt and general control register (index : 03h)) 5vdet/gpi pin status change for memory card : pc card status change : cd1# and/or cd2# pin status change bvd1 and/or bvd2 pin status change ready#/busy# pin status change 5vdet/gpi pin status change as shown above, interrupt sources fall into two types : interrupts derived from the ireq# pin and the pc card status change. meanwhile, interrupt output destinations available on the isa bus are the irqn pins (n = 3, 4, 5, 7, 9, 10, 11, 12, 14, and 15), the intr# pin, and the ri_out# pin (only for interrupts derived from the cd1# and/or cd2# pin status change as specified by bit4 (card detect resume enable bit) in the card detect and general control register (index : 16h)). some of the internal registers provide the following four types of interrupt control : (1) control over interrupt sources (2) control over interrupt output destinations (3) control over interrupt output waveforms (4) control over interrupt cancellation of the above four types of interrupt control, (1) control over interrupt sources is described in ?. card slot pin status indication and register setting?while the other three types are described below. 4. interrupt pr ocessing
rf5c296/rf5c396l/RB5C396/rf5c396 63 interrupts derived from the ireq# pin particularly for the i/o card can be assigned to the irqn pins as their out - put destinations by setting bits3 to 0 in the interrupt and general control register (index : 03h) as shown in the first table on the next page. interrupts derived from the pc card status change for both the i/o card and the memory card can be assigned to the irqn pins or the intr# pin as their output destinations by setting bits7 to 4 in the card status interrupt configuration register (index : 05h) or bit4 (intr# enable bit) in the interrupt and general control register (index : 03h) as shown in the second table on the next page. incidentally, the irqn pins are caused to transition to high impedance unless assigned as interrupt output desti - nations. as described above, interrupts derived from the cd1# and/or cd2# pin status change among interrupts derived from the pc card status change can be assigned to the ri_out# pin as their output destination. more specifically, the ri_out# pin output can be generated upon occurrence of the cd1# and/or cd2# pin sta - tus change by setting bit4 (card detect resume enable bit) to ??in the card detect and general control register (index : 16h) and then setting bit3 (card detect enable bit) to ??in the card status interrupt configuration register (index : 05h). for details on these registers, see their respective description in ?nternal registers? 4.1 contr ol o ver interrupt output destinations
rf5c296/rf5c396l/RB5C396/rf5c396 64 bit3 bit2 bit1 bit0 irqn selection 0 0 0 0 irq not selected 0 0 1 1 irq3 enabled 0 1 0 0 irq4 enabled 0 1 0 1 irq5 enabled 0 1 1 1 irq7 enabled 1 0 0 1 irq9 enabled 1 0 1 0 irq10 enabled 1 0 1 1 irq11 enabled 1 1 0 0 irq12 enabled 1 1 1 0 irq14 enabled 1 1 1 1 irq15 enabled intr# enable bit bit7 bit6 bit5 bit4 irqn selection 0 0 0 0 0 irq not selected 0 0 0 1 1 irq3 enabled 0 0 1 0 0 irq4 enabled 0 0 1 0 1 irq5 enabled 0 0 1 1 1 irq7 enabled 0 1 0 0 1 irq9 enabled 0 1 0 1 0 irq10 enabled 0 1 0 1 1 irq11 enabled 0 1 1 0 0 irq12 enabled 0 1 1 1 0 irq14 enabled 0 1 1 1 1 irq15 enabled 1 redirected to intr# ?output destination settings for interrupts derived from ireq# ?output destination setting for interrupts derived from pc card status change
rf5c296/rf5c396l/RB5C396/rf5c396 65 interrupts derived from the irqn pins represent different output waveforms in the level mode and the edge mode. in the level mode, the irqn pin outputs are caused to transition from high impedance to ??upon interrupt generation and vice versa upon completion of interrupt processing. in the edge mode, the irqn pin outputs are caused to transition from low level to ??upon interrupt generation and vice versa upon completion of interrupt pro - cessing. the level mode and the edge mode can be specified by setting bit1 (level mode interrupt enable bit) to ??and ?? respectively, in the global control register (index : 1eh). of the irqn pin outputs, the irq14 pin output alone allows exceptional waveform control, which can be specified by setting bit3 (irq14 pulse mode enable bit) to ??in the global control register (index : 1eh). namely, inter - rupts derived from the irq14 pin represent output waveforms in the level mode even when the edge mode is spec - ified by setting bit1 (level mode interrupt enable bit) to ??in the global control register (index : 1eh). meanwhile, the intr# pin output is caused to transition from high level to ??for the duration of three clock pulses upon interrupt generation and vice versa upon completion of interrupt processing. interrupts derived from the ireq# pin can be canceled by first canceling interrupts on the pc card bus with the ireq# pin caused to transition to low level and then canceling interrupts on the isa bus with the ireq# pin caused to transition to ?? interrupts derived from the pc card status change can be canceled by the following two methods : (1) reading the card status change register (index : 04h) (2) setting applicable bits to ??in the card status change register (index : 04h) provided that bit2 (explicit write back card status change acknowledge bit) is set to ??in the global control register (index : 1eh). the rf5c296 and the rf5c396 have the function of indicating the status of the pins on the pc card slot in vari - ous forms to the cpu. this function falls into the following four types : (1) reading back the pins on the pc card slot (2) making settings upon occurrence of any pin status change on the pc card slot (3) generating interrupts upon occurrence of any pin status change on the pc card slot (4) performing other processes upon occurrence of any pin status change on the pc card slot the internal registers contained in the rf5c296 and the rf5c396 are grouped according to their functions to facilitate such processes as interrupt processing. while the internal registers are described in detail under classifi - cation by function in ?nternal registers? they are described briefly under classification by pin on the pc card slot in this section. 5. car d slot pin status indication and register setting 4.3 contr ol o ver interrupt cancellation 4.2 contr ol o ver interrupt output w a vef orms
rf5c296/rf5c396l/RB5C396/rf5c396 66 the cd1# and cd2# pins are grounded within the pc card and pulled up on the pc card slot. both the cd1# and cd2# pins are caused to transition to ??upon insertion of the pc card into the pc card slot. note that some of the internal registers are designed to control the cd1# and cd2# pins upon occurrence of both the cd1# and cd2# status change and others upon occurrence of either the cd1# or cd2# status change. ? interface status register (index : 01h) : bit3 (for the cd2# pin) and bit2 ( for the cd1# pin) these bits can be used to specify reading back of the cd1# and cd2# pin inputs. ? card status change register (index : 04h) : bit3 (card detect change bit) this bit will be set to ??upon occurrence of either the cd1# or cd2# pin status change (insertion or removal of the pc card into or from the pc card slot). ?card status interrupt configuration register (index : 05h) : bit3 (card detect enable bit) this bit can be used to specify generation of interrupts from the irqn pins or the intr# pin upon occurrence of either the cd1# or cd2# pin status change. ?card detect and general control register (index : 16h) : bit4 (card detect resume enable bit) this bit can be used to specify generation of interrupts from the ri_out# pin upon occurrence of either the cd1# or cd2# pin status change. ?card detect and general control register (index : 16h) : bit5 (software card detect interrupt bit) this bit can be set to ??to specify software-controlled generation of interrupts derived from the cd1# and/orcd2# pin status change. ?card detect and general control register (index : 16h) : bit1 (configuration reset enable bit) this bit can be set to ??to specify generation of reset pulses upon transition of both the cd1# and cd2# pins to ??(removal of the pc card from the pc card slot), thus resetting the internal registers relating to address windows or interrupts. (for details on the internal registers thus reset, see ?. chip control?in ?nternal registers?) 5.1 cd1# and cd2# pins
rf5c296/rf5c396l/RB5C396/rf5c396 67 the stschg#/ri# pin functions as an input pin for the card status change# and ring indicate# signals when the pc card is the i/o card (bit5 is set to ??in the interrupt and general control register (index : 03h)). the internal registers described below also function as those relating to the stschg#/ri# pin status on the con - dition that the pc card is the i/o card. ?interface status register (index : 01h) : bit0 (battery voltage detect 1 bit) this bit can be used to specify reading back the stschg#/ri# pin. ?card status change register (index : 04h) : bit0 this bit will be set to ??upon transition of the card status change# and ri# signals to ??when bit7 (ring indicate enable bit) is set to ??in the interrupt and general control register (index : 03h). ?interrupt and general control register (index : 03h) : bit7 (ring indicate enable bit) this bit can be set to ??to specify output of the ring indicate# signal to the ri_out# pin. ?interface status register (index : 01h) : bit1 ( for the bvd2 pin) and bit0 (for the bvd1 pin) these bits can be used to specify reading back the bvd1 and bvd2 pins. ?card status change register (index : 04h) : bits1 and 0 bit1 will be se to ??upon detection of the battery warning condition, respectively. bit0 will be set to ??upon detection of the battery dead condition, respectively. ?card status interrupt configuration register (index : 05h) : bit1 and bit0 bit1 can be set to ??to specify generation of interrupts upon detection of the battery warning conditions, respectively. bit0 can be set to ??to specify generation of interrupts upon detection of the battery dead conditions, respec - tively. the bvd1 and bvd2 pins function as input pins for battery voltage detection when the pc card is the memory card (bit5 is set to ??in the interrupt and general control register (index : 03h)). based on output signals from the pc card, the bvd1 and bvd2 pin signals are defined as shown in the table below : bvd1 0 0 1 1 bvd2 0 1 0 1 battery voltage conditions faulty battery voltage conditions requiring battery replacement and not guar - anteeing data retention. faulty battery voltage conditions requiring battery replacement and not guar - anteeing data retention. faulty battery voltage conditions requiring battery replacement but guaran - teeing data retention. normal battery voltage conditions. 5.2 bvd1 and bvd2 pins 5.3 stschg#/ri# pin
rf5c296/rf5c396l/RB5C396/rf5c396 68 the gpi pin, as its full name ?eneral-purpose input pin?suggests, functions as an input pin for general purpose use. further, it can also be connected to the vs1# pin on the pc card slot to detect the 5v pc card. (for details, see ?.2 5vdet/gpi and vs1# pins?in ?. connections to pcmcia slot?in ?ardware design considera - tions?) ?interface status register (index : 01h) : bit7 this bit can be used to specify reading back the 5vdet/gpi pin. ?card status change register (index : 04h) : bit4 (gpi change bit) this bit will be set to ??upon generation of interrupts derived from the gpi pin status change when bit2 (gpi enable bit) is set to ??in the card detect and general control register (index : 16h). ?card detect and general control register (index : 16h) : bit3 (gpi transmission control bit) this bit can be set to ??and ??to specify generation of interrupts upon transition of the gpi pin from ??to ??and vice versa, respectively. ?card detect and general control register (index : 16h) : bit2 (gpi enable bit) this bit can be used to enable interrupts from the gpi pin and set to ??to specify generation of interrupts upon the gpi input status change. the internal registers described below function as those relating to the ready#/busy# pin status on the condi - tion that the pc card is the memory card. ?interface status register (index : 01h) : bit5 (ready/busy# bit) this bit can be set to ??and ??to specify reading back the ready#/busy# pins, respectively (specify read - ing back the ireq# pin when the pc card is the i/o card). ?card status change register (index : 04h) : bit2 (ready change bit) this bit will be set to ??upon transition of the ready#/busy# pins from ??to ?? ?card status interrupt configuration register (index : 05h) : bit2 (ready enable bit) this bit can be set to ??to specify generation of interrupts upon transition of the ready#/busy# pins from ??to ?? 5.5 read y#/b usy# pins 5.4 5vdet/gpi pin
rf5c296/rf5c396l/RB5C396/rf5c396 69 wp pin ?interface status register (index : 01h) : bit4 (memory write protect bit) this bit an be used to specify reading back the wp pin. note that write protection will not be enabled even when the wp pin is set to ??unless write protect bit is set to ??for each memory address window. power supply status ?interface status register (index : 01h) : bit6(pc card power active bit) this bit an be used to indicate the status of power supply to the pc card slot and set to ??and ??to indicate the power-off state (in which both the vcc3ven# and vcc5ven# pins are held at high level) and the power- on state, respectively. 5.6 other pins
symbol item condition ratings unit v cc power supply voltage gnd=0v ?.3 to 7 v vte terminal voltage gnd=0v ?.3 to v cc +0.3 v topr operating temperature ?0 to +85 ?c tstg storage temperature ?5 to +125 ?c rf5c296/rf5c396l/RB5C396/rf5c396 70 absolute maximum ra tings absolute maximum ratings absolute maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions. moreover, such values for any two items must not be reached simultaneously. operation above these absolute maximum ratings may cause degradation or permanent damage to the device. these are stress ratings only and do not necessarily imply functional operation below these limits.
rf5c296/rf5c396l/RB5C396/rf5c396 71 dc electrical chara cteristics (vcc=5v) symbol item measuring condition limits min. typ. max. unit v ih v il v oh1 * 1 v oh2 * 2 v oh3 * 3 v ol1 * 1 v ol2 * 2 v ol3 * 3 v ol4 * 4 i ilk i il1 * 5 i il2 * 6 i il3 * 7 i oz iccstd i cc ??input voltage ??input voltage ??output voltage ??output voltage ??output voltage ??output voltage ??output voltage ??output voltage ??output voltage input leakage current input current (pull-up) input current (pull-down) input current (pull-down) off output leakage current stand-by current operating current i oh =?2ma i oh =?ma i oh =?ma i ol =12ma i ol =8ma i ol =4ma i ol =16ma v in =0 to v cc v in =0 v in =v cc v in =v cc v out =0 to v cc v in =0v or v cc v in =0v or v cc (v cc =5v) v cc , fsysclk=10mhz 2.0 ?.3 2.4 2.4 2.4 ?0 ?00 ?0 ?0 25 50 rf5c296 rf5c396 v cc +0.3 0.8 0.4 0.4 0.4 0.4 +10 100 200 +10 10 12 20 v v v v v v v v v a a a a a a ma vcc=5v 10%, ta=0 to 70?c * 1) sd15 to sd0, zerows# * 2) irqn, ca25 to ca0, cd15 to cd0, ce1#, ce2#, ciord#, ciowr#, oe#, we# * 3) spkrout#, ri_out#, intr#, gpi, vcc3en#, vcc5en#, vpp_en0, vpp_en1, reg#, reset * 4) iocs16#, memcs16#, iochrdy * 5) gpi * 6) cd15 to cd0 * 7) resetdrv
rf5c296/rf5c396l/RB5C396/rf5c396 72 vcc=3.3v 0.3v, ta=0 to 70?c symbol item measuring condition limits min. typ. max. unit v ih v il v oh1 * 1 v oh2 * 2 v oh3 * 3 v ol1 * 1 v ol2 * 2 v ol3 * 3 v ol4 * 4 i ilk i il1 * 5 i il2 * 6 i il3 * 7 i oz iccstd i cc ??input voltage ??input voltage ??output voltage ??output voltage ??output voltage ??output voltage ??output voltage ??output voltage ??output voltage input leakage current input current (pull-up) input current (pull-down) input current (pull-down) off output leakage current stand-by current operating current i oh =?ma i oh =?ma i oh =?ma i ol =6ma i ol =4ma i ol =2ma i ol =8ma v in =0 to v cc v in =0 v in =v cc v in =v cc v out =0 to v cc v in =0v or v cc v in =0v or v cc (v cc =3.3v) v cc , fsysclk=10mhz 2.0 ?.3 2.4 2.4 2.4 ?0 ?00 ?0 ?5 10 25 rf5c296 rf5c396 v cc +0.3 0.6 0.4 0.4 0.4 0.4 +10 50 100 +10 10 6 10 v v v v v v v v v a a a a a a ma * 1) sd15 to sd0, zerows# * 2) irqn, ca25 to ca0, cd15 to cd0, ce1#, ce2#, ciord#, ciowr#, oe#, we# * 3) spkrout#, ri_out#, intr#, gpi, vcc3en#, vcc5en#, vpp_en0, vpp_en1, reg#, reset * 4) iocs16#, memcs16#, iochrdy * 5) gpi * 6) cd15 to cd0 * 7) resetdrv dc electrical chara cteristics (vcc=3.3v)
sysclk ??pulse width sysclk ??pulse width la <23 : 17> setup time to bale falling bale pulse width la <23 : 17> hold time from bale la <23 : 17>, sa <17 : 12>, sa0 and sbhe# setup time to memr#, memw# memr#, memw# active to falling edge of sysclk sa <16 : 0> and sbhe# hold from memr#, memw# memcs16# valid from la <23 : 17> memcs16# valid from sa <16 : 12> memcs16# hold from la <23 : 17> memcs16# tri-state from sa <16 : 12> memcs16# tri-state from la <23 : 17> iochrdy active from falling edge of sysclk iochrdy low from memr#, memw# zerows# active from sa <16 : 12> zerows# hold from memr#, memw# zerows# tri-state from sa <16 : 12> zerows# tri-state from memr#, memw# wait# active to iochrdy inactive wait# inactive to iochrdy active ca <25 : 0> valid delay from la <23 : 17>, sa <16 : 0> ca <25 : 0> hold from la <23 : 17>, sa <16 : 0> oe#, we# valid from memr#, memw# with memory delay inhibit oe#, we# valid from memr#, memw# 16bit windows oe#, we# valid from memr#, memw active ce#, reg# valid from la <23 : 17>, sa <16 : 0> rf5c296/rf5c396l/RB5C396/rf5c396 73 symbol item limits min. max. unit tckl tckh t1 t2 t3 t7a t35 t12 t5a t5b t6a t6b t6c t21a t20 t17 t29a t29b t29c t41 t42 t30a t40 t32a t32b t38 t31 40* 1 24(35) * 1 24(35) 40 24(35)* 1 32* 1 60 55 35 20(30)* 1 20(30)* 1 50 27 t35+28 24 47(55) a c electrical chara cteristics 45 45 45 50 15 23 15 25 0 0 0 5 t35 0 v cc =5v 10%(3.3v 0.3v)* 2 , ta=0 to 70?c, cl=100pf ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1. 8/16bit memor y cyc le
rf5c296/rf5c396l/RB5C396/rf5c396 74 symbol item limits min. max. unit t39 t71 t72 t73 t74 t75 t76 ce#, reg# invalid from la <23 : 17>, sa <16 : 0> cd <23 : 17> valid delay from sd <15 : 0> when i/o read sd <15 : 0> hold from memr# cd <15 : 0> active from la <23 : 17>, sa <16 : 0> cd <15 : 0> valid delay from sd <15 : 0> when i/o write sd <15 : 0> setup time from falling edge of memw# sd <15 : 0> hold time from memw# ns ns ns ns ns ns ns 0 10 0 25 47 (55) 50 47 (55) 50 v cc =5v 10%(3.3v 0.3v)* 2 , ta=0 to 70?c, cl=100pf * 1) this timing assumes a load capacitance of 50pf. * 2) in the above table, the parenthesized specifications apply when vcc=3.3 0.3v. accordingly, the non-parenthesized specifications alone apply whether vcc=5v 10% or 3.3 0.3v.
rf5c296/rf5c396l/RB5C396/rf5c396 75 t c k 1 t c k h t 1 t 3 t 2 a d d r e s s v a l i d v a l i d t 7 2 t 7 1 t 1 2 t 7 6 t 7 5 t 7 a d a t a v a l i d t 2 1 a t 2 9 b t 2 9 a , t 2 9 c t 6 b t 6 a , t 6 c t 5 b t 2 0 t 4 1 t 3 0 a t 7 4 t 7 3 t 3 1 t 3 2 a , t 3 2 b t 4 2 t 4 0 t 7 4 t 3 8 t 3 9 t 7 3 t 1 7 a d d r e s s v a l i d d a t a v a l i d d a t a v a l i d s y s c l k l a ( 2 3 , 1 7 ) b a l e s a ( 1 6 , 0 ) s b h e # s d ( 1 5 , 0 ) ( r e a d d a t a ) s d ( 1 5 , 0 ) ( w r i t e d a t a ) m e m r # , m e m w # m e m c s 1 6 # i o c h r d y z e r o w s # w a i t # c a d r ( 2 5 , 0 ) c d ( 1 5 , 0 ) ( r e a d d a t a ) c d ( 1 5 , 0 ) ( w r i t e d a t a ) o e # , w e # c e 1 # , c e 2 # , r e g # t 5 a t 3 5 ?8/16bit memory cycle
rf5c296/rf5c396l/RB5C396/rf5c396 76 symbol item limits min. max. unit t1 t2 t45 t46 t7 t12 t5a t5b t19a t19b t20 t21 t41 t42 t28 t29a t29c t30b t40 t33 t38 t31a t31b t39 t34 v cc =5v 10% (3.3v 0.3v)* 2 , ta=0 to 70?c, cl=100pf 2. 8/16bit i/o cyc le la <23 : 17> setup time from to bale falling bale pulse width aen setup time to ior#, iow# aen hold time to ior#, iow# la <23 : 17>, sa <17 : 0> and sbhe setup time to ior#, iow# iocs16# hold time from sa <15 : 0> iocs16# active from la <23 : 17> iocs16# active from sa <16 : 0> iocs16# hold time from sa <15 : 0> iocs16# tri-state from sa <15 : 0> iochrdy low from ior#, iow# iochrdy active from falling edge of sysclk wait# active to iochrdy inactive wait# inactive to iochrdy active zerows# active from 8bit ior#, iow# zerows# hold time from ior#, iow# zerows# tri-state from ior#, iow# active ca <25 : 0> valid delay from la <23 : 17>, sa <17 : 0> ca <25 : 0> hold time from la <23 : 17>, sa<17 : 0> ciord#, ciowr# valid from ior#, iow# ciord#, ciowr# inactive from ior#, iow# inactive ce#, reg# valid from la <23 : 17>, sa <17 : 0> ce#, reg# valid from sa <15 : 0> i/o with iois16# generated ce#, reg# invalid from la <23 : 17>, sa <17 : 0> ca <25 : 0> to iois16# 45 50 45 25 45 25 0 0 0 5 0 0 40 24(35) 40 32 * 1 24(35)* 1 20(30)* 1 20(30) * 1 25 (35) 35 50 25 24 47 (55) 75 45 (55) 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns * 1) this timing assumes a load capacitance of 50pf. * 2) in the above table, the parenthesized specifications apply when v cc =3.3 0.3v. accordingly, the non-parenthesized specifications alone apply whether v cc =5v 10% or 3.3 0.3v.
rf5c296/rf5c396l/RB5C396/rf5c396 77 note 50 45 (55) 50 ns ns ns ns ns ns 10 0 25 symbol item limits min. max. unit setup time of data to falling edge of ciowr# (tdsu) depends on setup time of address to iow# of system (stdsu). tdsu (min.)=stdsu-30ns.m t71 t72 t73 t74 t75 t76 * 1) this timing assumes a load capacitance of 50pf. * 2) in the above table, the parenthesized specifications apply when v cc =3.3 0.3v. accordingly, the non-parenthesized specifications alone apply whether v cc =5v 10% or 3.3 0.3v. cd <15 : 0> valid delay from sd <15 : 0> when i/o read sd <15 : 0> hold time ior# cd <15 : 0> active from la <23 : 17>, sa <17 : 0> cd <15 : 0> valid delay from sd <15 : 0> when i/o read sd <15 : 0> setup time to iow# active sd <15 : 0> hold time iow#
rf5c296/rf5c396l/RB5C396/rf5c396 78 a d d r e s s v a l i d t c k 1 t c k h t 1 t 2 t 4 6 t 4 5 t 7 1 t 7 2 t 7 5 t 2 0 t 2 1 t 4 2 t 4 1 t 2 8 t 7 3 t 7 3 t 3 8 t 3 3 t 3 4 t 3 9 t 7 4 t 7 4 t 4 0 t 7 t 3 5 t 7 6 t 1 2 t 1 9 a , t 1 9 b t 2 9 a , t 2 9 b t 3 1 a , t 3 1 b a d d r e s s v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d v a l i d t 5 a t 5 b s y s c l k l a ( 2 3 , 1 7 ) b a l e a e n s a ( 1 6 , 0 ) s b h e # s d ( 1 5 , 0 ) ( r e a d d a t a ) s d ( 1 5 , 0 ) ( w r i t e d a t a ) i o r # , i o w # i o c s 1 6 # i o c h r d y z e r o w s # w a i t # c a d r ( 2 5 , 0 ) c d ( 1 5 , 0 ) ( r e a d d a t a ) c d ( 1 5 , 0 ) ( w r i t e d a t a ) c i o r d # , c i o w r # c e 1 # , c e 2 # , r e g # i o i s 1 6 # t 3 0 b ?8/16bit i/o cycle
rf5c296/rf5c396l/RB5C396/rf5c396 79 symbol item limits min. max. unit sa <16 : 0>, sbhe# setup time aen setup time aen hold time i/o command pulse width sd <7 : 0> write data setup time sd <7 : 0> write data hold time sd <7 : 0> read data delay sd <7 : 0> read data hold time cs# setup time cs# hold time ns ns ns ns ns ns ns ns ns ns 45 45 25 100 40 10 0 100 0 70 v cc =5v 10%(3.3v 0.3v),ta=0 to 70?c, cl=100pf a d d r e s s v a l i d a d d r e s s v a l i d t 1 t 8 0 t 8 1 t 8 2 t 8 3 t 8 4 t 8 6 t 8 8 t 8 9 t 8 7 t 8 5 l a ( 2 3 , 1 7 ) b a l e s a ( 1 6 , 0 ) s b h e # a e n i o w # i o r # s d 7 t o 0 ( w r i t e ) s d 7 t o 0 ( r e a d ) c s # s y s c l k 3. internal 8bits register access cyc le t80 t81 t82 t83 t84 t85 t86 t87 t88 t89
rf5c296/rf5c396l/RB5C396/rf5c396 80 symbol item limits min. max. unit ri# to ri_out# delay, spkr# to spkrout# delay card status change, intr# valid delay card status change, irqn valid delay intr# pulse width ireq# to irqn delay ns ns ns ns ns 3 tclkp* 2 30 2 tclkp* 2 50 50 s t s c h g # / r i # c a t d s t a t u s c h a n g e i r e q # i n t r # i r q # r i _ o u t # s p k r # s p k r o u t # t 5 0 t 5 1 t 5 2 t 5 4 t 5 3 t 5 4 t 5 0 t 5 0 t 5 0 v cc =5v 10%(3.3v 0.3v)* 1 ,ta=0 to 70?c, cl=100pf t50 t51 t52 t53 t54 * 1) in the above table, the parenthesized specifications apply when v cc =3.3 0.3v. accordingly, the non-parenthesized specifications alone apply whether v cc =5v 10% or 3.3 0.3v. * 2) tclkp means the clock cycle period. 4. interrupt, ring indicate speaker
rf5c296/rf5c396l/RB5C396/rf5c396 81 symbol item limits min. max. unit t60 t61 resetdrv setup time to powergood ns ns 200 5 resetdrv falling edge from rising edge powergood v cc =5v 10%(3.3v 0.3v),ta=0 to 70?c, cl=100pf t 6 0 t 6 1 p o w e r g o o d r e s e t d r v 5. reset fr om po wergood
rf5c296/rf5c396l/RB5C396/rf5c396 82 symbol item limits min. max. unit iochrdy inactive from wait# active iochrdy active to wait# inactive ciowe# active from iow# iow# inactive to rising edge of ciowr#, tc (we#) sd <15 : 0> valid to cd <15 : 0> valid dack# (irq9) active to dma cycle begin system tc (irq11 or irq15) to card tc (we#) rising edge of dack# (irq9) to ce#, reg# 0 0 20(30)* 1 20(30)* 1 25 24 50 40 (50) 40 (50) 40 (50) v cc =5v 10%(3.3v 0.3v)* 2 , ta=0 to 70?c, cl=100pf i r q 9 ( d a c k # ) s d ( 1 5 , 0 ) i o w # i o c h r d y c i o r d # , o e # ( h i g h ) r e g # ( d a c k # t o c a r d ) c e 1 # , c e 2 # t 9 1 t 4 1 t 7 4 t 3 3 t 9 3 t 4 2 t 7 4 t 3 8 t 9 2 c d ( 1 5 , 0 ) c i o w r # w a i t # i r q 1 1 o r i r q 1 5 ( t c f r o m s y s t e m ) w e # ( t c t o c a r d ) d a t a v a l i d d a t a v a l i d 6. dma read cyc le timing t41 t42 t33 t38 t74 t91 t92 t93 ns ns ns ns ns ns ns ns * 1) this timing assumes a load capacitance of 50pf. * 2) in the above table, the parenthesized specifications apply when v cc =3.3 0.3v. accordingly, the non-parenthesized specifications alone apply whether v cc =5v 10% or 3.3 0.3v.
rf5c296/rf5c396l/RB5C396/rf5c396 83 v cc =5v 10%(3.3v 0.3v)* 2 , ta=0 to 70?c, cl=100pf symbol item limits min. max. unit iochrdy inactive from wait# active iochrdy active from wait# inactive ciord# active from ior# ior# inactive to rising edge of ciord#, tc (oe#) sd <15 : 0> valid to cd <15 : 0> valid sd <15 : 0> hold from ior#, memr# dack# (irq9) active to dma cycle begin system tc (irq11 or irq15) to card tc (we#) rising edge of dack# (irq9) to ce#, reg# 0 0 10 20(30)* 1 20(30)* 1 25 24 50 40 (50) 40 (50) 40 (50) i r q 9 ( d a c k # ) s d ( 1 5 , 0 ) i o r # i o c h r d y c i o w r # , w e # ( h i g h ) r e g # ( d a c k # t o c a r d ) c e 1 # , c e 2 # t 9 4 t 7 1 t 3 8 t 4 2 t 9 6 t 7 2 t 4 1 t 3 3 t 9 5 c d ( 1 5 , 0 ) c i o r d # w a i t # i r q 1 1 o r i r q 1 5 ( t c f r o m s y s t e m ) o e # ( t c t o c a r d ) d a t a v a l i d d a t a v a l i d t41 t42 t33 t38 t71 t72 t94 t95 t96 ns ns ns ns ns ns ns ns ns * 1) this timing assumes a load capacitance of 50pf. * 2) in the above table, the parenthesized specifications apply when v cc =3.3 0.3v. accordingly, the non-parenthesized specifications alone apply whether v cc =5v 10% or 3.3 0.3v. 7. dma write cyc le timing
notice rf5c296/rf5c396l/RB5C396/rf5c396 84 for the rf5c296 and the rf5c396, the relation between the read/write timings for the data and address sig - nals and those for the ciowr#, ciord#, we#, and oe# signals is not specified, and dependent on the input timings for the relevant signals from the system bus and on the internal delay time of the named signals. it is recommended that the above should be included in the considerations of timing conditions for the jeida4.2 (or pcmcia2.1) system. symbol item limits min. max. unit t97 dma request from card to system ns 40 v cc =5v 10%(3.3v 0.3v), ta=0 to 70?c, cl=100pf i r q 1 0 ( d r e q t o s y s t e m ) i n p a c k # , s p k p # , o r i o i s 1 6 # t 9 7 ( d r e q o r d r e q # f r o m c a r d ) 8. dma request timing
rf5c296/rf5c396l/RB5C396/rf5c396 85 b us system suppor t envir onment i s a b a s a d d r e s s a d d r e s s c o n t r o l d a t a r f 5 c 2 9 6 r f 5 c 3 9 6 l r f 5 c 3 9 6 c a r d s l o t p w r c t r l p o w e r s w i t c h i n g c o n t r o l d a t a ?driver soft phoenix technologies,ltd.(u.s.a.) phoenixcard manager plus tm systemsoft corporation(u.s.a.) systemsoft's card soft tm ?demonstration board demonstration board for rf5c396
rf5c296/rf5c396l/RB5C396/rf5c396 86 p a cka ge dimensions ?rf5c296 144pin lqfp (lqfp-144-p1) ?rf5c396l 208pin lqfp (lqfp-208-p1) 0 ? t o 1 0 2 2 0 . 4 0 . 8 6 6 0 . 0 1 6 2 0 t y p . 0 . 7 8 7 t y p . 2 2 0 . 4 0 . 8 6 6 0 . 0 1 6 2 0 t y p . 0 . 7 8 7 t y p . 7 2 7 3 1 0 8 1 0 9 1 4 4 3 7 3 6 1 0 . 2 0 . 1 0 . 0 0 8 0 . 0 0 4 0 . 1 5 0 . 0 5 0 . 0 0 6 0 . 0 0 2 1 . 0 t y p . 0 . 0 3 9 t y p . 0 . 5 0 . 2 0 . 0 2 0 0 . 0 0 8 1 . 5 + 0 . 2 0 . 1 5 0 . 0 5 9 + 0 . 0 0 8 0 . 0 0 6 0 m i n . 0 m i n . 1 . 7 m a x . 0 . 0 6 7 m a x . u n i t : m m i n c h 0 . 1 ( 0 . 0 0 4 ) 0 . 5 0 . 0 2 0 0 . 1 5 ( 0 . 0 0 6 ) m 0 ? t o 1 0 ? 3 0 . 0 0 . 4 1 . 1 8 1 0 . 0 1 6 2 8 . 0 t y p . 1 . 1 0 2 t y p . 1 0 4 5 3 1 2 0 8 1 5 7 1 0 5 3 0 . 0 0 . 4 1 . 1 8 1 0 . 0 1 6 2 8 . 0 t y p . 1 . 1 0 2 t y p . 0 . 2 0 . 1 0 . 0 0 8 0 . 0 0 4 0 . 1 2 7 0 . 0 5 0 . 0 0 5 0 . 0 0 2 1 . 0 t y p . 0 . 0 3 9 t y p . 0 . 5 0 . 2 0 . 0 2 0 0 . 0 0 8 1 . 4 + 0 . 2 0 . 1 6 0 . 0 5 5 + 0 . 0 0 8 0 . 0 0 6 0 m i n . 0 m i n . 1 . 7 m a x . 0 . 0 6 7 m a x . 0 . 1 ( 0 . 0 0 4 ) 0 . 5 0 . 0 2 0 0 . 1 ( 0 . 0 0 4 ) m u n i t : m m i n c h
rf5c296/rf5c396l/RB5C396/rf5c396 87 1 9 . 5 t y p . 2 3 . 0 0 . 4 0 . 9 0 6 0 . 0 1 6 0 . 7 6 8 t y p . 2 3 . 0 0 . 4 0 . 9 0 6 0 . 0 1 6 1 9 . 5 t y p . 0 . 7 6 8 t y p . 4 c 1 . 1 5 ( 2 . 1 3 ) ( 0 . 0 8 4 ) 0 . 6 0 0 . 1 0 0 . 0 2 4 0 . 0 0 4 1 . 5 3 0 . 2 0 0 . 0 6 0 0 . 0 0 8 ( 0 . 3 6 ) ( 0 . 0 1 4 ) ( 1 . 1 7 ) ( 0 . 0 4 6 ) ( 0 . 7 8 0 . 1 0 ) ( 0 . 0 3 1 0 . 0 0 4 ) 0 . 2 5 ( 0 . 0 1 0 ) m a b c d e f g j k l m n p r t 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 ( 1 . 2 7 1 5 = 1 9 . 0 5 ) ( 0 . 0 5 1 5 = 0 . 7 5 ) 1 . 9 7 0 . 4 0 0 . 0 7 8 0 . 0 1 6 1 . 2 7 0 . 1 0 0 . 0 5 0 . 0 0 4 1 . 2 7 0 . 1 0 0 . 0 5 0 . 0 0 4 1 . 9 8 0 . 4 0 0 . 0 7 8 0 . 0 1 6 ( 1 . 2 7 1 5 = 1 9 . 0 5 ) ( 0 . 0 5 1 5 = 0 . 7 5 ) u n i t : m m i n c h h ?RB5C396 256pin pbga (bga-256-p1)
rf5c296/rf5c396l/RB5C396/rf5c396 88 3 0 . 0 0 . 4 1 . 1 8 1 0 . 0 1 6 2 8 . 0 t y p . 1 . 1 0 2 t y p . 1 0 4 5 3 5 2 1 2 0 8 1 5 7 1 5 6 1 0 5 3 0 . 0 0 . 4 1 . 1 8 1 0 . 0 1 6 2 8 . 0 t y p . 1 . 1 0 2 t y p . 0 . 1 5 0 . 1 5 0 . 0 0 6 0 . 0 0 2 0 . 2 0 . 1 0 . 0 0 8 0 . 0 0 4 1 . 0 t y p . 0 . 0 3 9 t y p . 0 . 5 0 . 2 0 . 0 2 0 0 . 0 0 8 0 ? t o 1 0 ? 3 . 3 5 + 0 . 2 0 . 1 6 0 . 1 3 2 + 0 . 0 0 8 0 . 0 0 6 0 m i n . 0 m i n . 3 . 8 m a x . 0 . 1 5 0 m a x . 0 . 1 ( 0 . 0 0 4 ) 0 . 5 0 . 0 2 0 0 . 1 ( 0 . 0 0 4 ) m u n i t : m m i n c h ?rf5c396 208pin qfp (qfp-208-p1)
ricoh company, ltd. electronic devices division headquarters 13-1, himemuro-cho, ikeda city, osaka 563, japan phone 81-727-53-1111 fax 81-727-53-6011 yokohama office (international sales) 3-2-3, shin-yokohama, kohoku-ku, yokohama city, kanagawa 222, japan phone 81-45-477-1697 fax 81-45-477-169 4 ?695 ricoh corporation electronic devices division san jose office 3001 orchard parkway, san jose, ca 95134-2088, u.s.a. phone 1-408-432-8800 fax 1-408-432-8375

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